[clang] fa0371f - [SveEmitter] Add builtins for SVE2 Floating-point integer binary logarithm instructions
Sander de Smalen via cfe-commits
cfe-commits at lists.llvm.org
Thu May 7 08:21:35 PDT 2020
Author: Sander de Smalen
Date: 2020-05-07T16:15:57+01:00
New Revision: fa0371f4fd97fe9f601991bb2341a1e0426173c6
URL: https://github.com/llvm/llvm-project/commit/fa0371f4fd97fe9f601991bb2341a1e0426173c6
DIFF: https://github.com/llvm/llvm-project/commit/fa0371f4fd97fe9f601991bb2341a1e0426173c6.diff
LOG: [SveEmitter] Add builtins for SVE2 Floating-point integer binary logarithm instructions
This patch adds builtins for:
- svlogb
Added:
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_logb.c
Modified:
clang/include/clang/Basic/arm_sve.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 6f436f7f9ff4..f1689d35582c 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1735,6 +1735,15 @@ def SVMLSLT_F_N : SInst<"svmlslt[_n_{d}]", "ddhR", "f", MergeNone, "aar
def SVMLSLT_F_LANE : SInst<"svmlslt_lane[_{d}]", "ddhhi", "f", MergeNone, "aarch64_sve_fmlslt_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
}
+////////////////////////////////////////////////////////////////////////////////
+// SVE2 - Floating-point integer binary logarithm
+
+let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
+def SVLOGB_M : SInst<"svlogb[_{d}]", "xxPd", "hfd", MergeOp1, "aarch64_sve_flogb">;
+def SVLOGB_X : SInst<"svlogb[_{d}]", "xPd", "hfd", MergeAnyExp, "aarch64_sve_flogb">;
+def SVLOGB_Z : SInst<"svlogb[_{d}]", "xPd", "hfd", MergeZeroExp, "aarch64_sve_flogb">;
+}
+
////////////////////////////////////////////////////////////////////////////////
// SVE2 - Contiguous conflict detection
let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_logb.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_logb.c
new file mode 100644
index 000000000000..ab0a508b5a27
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_logb.c
@@ -0,0 +1,112 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint16_t test_svlogb_f16_z(svbool_t pg, svfloat16_t op)
+{
+ // CHECK-LABEL: test_svlogb_f16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f16_z'}}
+ return SVE_ACLE_FUNC(svlogb,_f16,_z,)(pg, op);
+}
+
+svint32_t test_svlogb_f32_z(svbool_t pg, svfloat32_t op)
+{
+ // CHECK-LABEL: test_svlogb_f32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f32_z'}}
+ return SVE_ACLE_FUNC(svlogb,_f32,_z,)(pg, op);
+}
+
+svint64_t test_svlogb_f64_z(svbool_t pg, svfloat64_t op)
+{
+ // CHECK-LABEL: test_svlogb_f64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f64_z'}}
+ return SVE_ACLE_FUNC(svlogb,_f64,_z,)(pg, op);
+}
+
+svint16_t test_svlogb_f16_m(svint16_t inactive, svbool_t pg, svfloat16_t op)
+{
+ // CHECK-LABEL: test_svlogb_f16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> %inactive, <vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f16_m'}}
+ return SVE_ACLE_FUNC(svlogb,_f16,_m,)(inactive, pg, op);
+}
+
+svint32_t test_svlogb_f32_m(svint32_t inactive, svbool_t pg, svfloat32_t op)
+{
+ // CHECK-LABEL: test_svlogb_f32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f32_m'}}
+ return SVE_ACLE_FUNC(svlogb,_f32,_m,)(inactive, pg, op);
+}
+
+svint64_t test_svlogb_f64_m(svint64_t inactive, svbool_t pg, svfloat64_t op)
+{
+ // CHECK-LABEL: test_svlogb_f64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f64_m'}}
+ return SVE_ACLE_FUNC(svlogb,_f64,_m,)(inactive, pg, op);
+}
+
+svint16_t test_svlogb_f16_x(svbool_t pg, svfloat16_t op)
+{
+ // CHECK-LABEL: test_svlogb_f16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f16_x'}}
+ return SVE_ACLE_FUNC(svlogb,_f16,_x,)(pg, op);
+}
+
+svint32_t test_svlogb_f32_x(svbool_t pg, svfloat32_t op)
+{
+ // CHECK-LABEL: test_svlogb_f32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f32_x'}}
+ return SVE_ACLE_FUNC(svlogb,_f32,_x,)(pg, op);
+}
+
+svint64_t test_svlogb_f64_x(svbool_t pg, svfloat64_t op)
+{
+ // CHECK-LABEL: test_svlogb_f64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svlogb_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svlogb_f64_x'}}
+ return SVE_ACLE_FUNC(svlogb,_f64,_x,)(pg, op);
+}
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