[PATCH] D79478: [CodeGen][SVE] Lowering of shift operations with scalable types

[Kerry McLaughlin via Phabricator via cfe-commits]

kmclaughlin created this revision.
kmclaughlin added reviewers: sdesmalen, efriedma, ctetreau, huihuiz.
Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
kmclaughlin added a parent revision: D78812: [SVE][CodeGen] Fix legalisation for scalable types.

Adds AArch64ISD nodes for:

- SHL_PRED (logical shift left)
- SHR_PRED (logical shift right)
- SRA_PRED (arithmetic shift right)

Existing patterns for unpredicated left shift by immediate
have also been moved into the appropriate multiclasses
in SVEInstrFormats.td.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79478

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
  llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll

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