[PATCH] D78129: Add Marvell ThunderX3T110 support

[Sjoerd Meijer via Phabricator via cfe-commits]

SjoerdMeijer added a comment.

In D78129#2022307 <https://reviews.llvm.org/D78129#2022307>, @joelkevinjones wrote:

> In email Wei asked for help about he following error message:
>
>   error message from tblgen
>   Included from /home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64.td:439:
>   /home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td:961:5: error: 'CycloneModel' lacks information for 'AUTDZA'
>  
>   def DZA  : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>;
>   ^
>   In the end:
>   Incomplete schedule models found.
>  
>   ·         Consider setting 'CompleteModel = 0' while developing new models.
>   ·         Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.
>   ·         Instructions should usually have Sched<[...]> as a superclass, you may temporarily use an empty list.
>   ·         Instructions related to unsupported features can be excluded with list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the processor model.
>   error: Incomplete schedule model
>
>
> And the comment from the person on the email was to define the instruction. The instruction is defined, as evidenced when table gen is run to produce the record-list. The error message can be suppressed by defining CompleteModele = 0, but that isn't correct, as there are models for those instructions.
>
> However, I now note that at least In the output that Wei captured, it isn't complaining about the ThunderX3T110 model, but about Cyclone.


Hi Joel,
Thanks for your message, and apologies for not replying earlier to the updates; missed the notification.
I am now taking a closer at some changes I hadn't looked at. In the mean, some drive-by comments:

It is okay'ish to set `CompleteModel = 0` if you're not interested in describing all instructions. The other way is of course to add the missing instruction to the model.

But first things first. @chill commented earlier about predicates. I also don't think you need to add `HasV8_3a` for the reason Momchill described, and there is still one left AArch64InstrInfo.td.

And while I am still looking into this, let me ask the question what I am wondering: why do you need to change the other scheduling models? These instructions are always supported, as a NOP, or otherwise.


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https://reviews.llvm.org/D78129