[PATCH] D62368: Add support for Hygon Dhyana processor
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Mon Apr 27 09:06:43 PDT 2020
craig.topper added inline comments.
================
Comment at: compiler-rt/lib/scudo/scudo_utils.cpp:85
+ (Ecx == signature_HYGON_ecx);
+ if (!IsIntel && !IsAMD && !IsHygon)
return false;
----------------
fanjinke wrote:
> craig.topper wrote:
> > What's the rationale for the vendor check here anyway? Why isn't the bit in ecx sufficient?
> Using the cpuid instruction to get the vendor id will return the ASCII code of the vendor id, which is stored in the ebx,ecx,edx registers.
> The ASCII code in the Hygon CPU is "HygonGenuine", the ecx = "eniu".
> For better differentiation from other cpus in the future, by following AMD/Intel way, we use full ASCII code to identify Hygon CPU.
>
Sorry, my question was about why this was restricted to Intel/AMD in the first place. Why should this code need to be updated every time a new vendor comes along? Why isn’t checking for sse4.2 regardless of vendor sufficient.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D62368/new/
https://reviews.llvm.org/D62368
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