[PATCH] D77872: [AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics

Sat Apr 25 06:51:57 PDT 2020

LukeGeeson marked an inline comment as done.
LukeGeeson added inline comments.

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Comment at: llvm/lib/Target/ARM/ARMInstrNEON.td:4846
+      VDOT<op6, op4, op23, RegTy, Asm, AsmTy, AccumTy, InputTy, OpNode> {
+  let hasNoSchedulingInfo = 1;
+
----------------
dmgreen wrote:
> I don't think that hasNoSchedulingInfo is necessarily the best way to handle this. That flag is intended for instructions that will never be scheduled, like Pseudo instructions.
> 
> If you are running into "Complete Schedule" problems, they might need HasMatMulInt8 added to the list of unsupported features instead.
Since there are no 8.6a cpus in llvm that support this extension, the default behaviour is to use Cortex-A57 scheduling - this also has no notion of 8.6a matmul.

This falls back to SchedMachineModel in `llvm/lib/Target/ARM/ARMScheduleA57.td` and in particular UnsupportedFeatures would be a candidate place to put unsupported features like matmul. I took issue with putting all new extensions here because there should be a separation of concerns between a particular scheduling model, and supporting new behaviour (which could go in a generic catch all location that might be slightly more informative ).

Did you have something in particular in mind?

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https://reviews.llvm.org/D77872