[PATCH] D78252: [AArch64] FMLA/FMLS patterns improvement.

Thu Apr 23 15:48:49 PDT 2020

ilinpv marked an inline comment as done.
ilinpv added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8058
+  def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
+                           (AArch64duplane16 (v8f16 V128:$Rm),
+                                           VectorIndexH:$idx))),
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ab wrote:
> ilinpv wrote:
> > ab wrote:
> > > Should this be V128_lo?  I don't think this is encodable for Rm in V16-V31  (same in the other indexed f16 variants I think)
> > Yep, I double checked encoding, you are right. Thank you very much for this. Fixed in 4eca1c06a4a9183fcf7bb230d894617caf3cf3be
> Thanks Pavel!  I think this applies to the `AArch64dup` variants too, which does entail adding `FPR16Op_lo` and `FPR16_lo` I imagine, and maybe a couple more
Oops. Thanks again, fix landed cc457672e628846c20e92c6e0a82896f0d6db031

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78252/new/

https://reviews.llvm.org/D78252