[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 259494.
HsiangKai added a comment.

- Address @simoncook's comments.
- Reorder instructions according to "V" specification.
- Add pseudo instructions in "V" specification.
- Add comments in RISCVInstrInfoV.td
- "V" implies "F".


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSchedRocket32.td
  llvm/lib/Target/RISCV/RISCVSchedRocket64.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/MC/RISCV/rvv/add.s
  llvm/test/MC/RISCV/rvv/and.s
  llvm/test/MC/RISCV/rvv/clip.s
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/convert.s
  llvm/test/MC/RISCV/rvv/div.s
  llvm/test/MC/RISCV/rvv/fadd.s
  llvm/test/MC/RISCV/rvv/fcompare.s
  llvm/test/MC/RISCV/rvv/fdiv.s
  llvm/test/MC/RISCV/rvv/fmacc.s
  llvm/test/MC/RISCV/rvv/fminmax.s
  llvm/test/MC/RISCV/rvv/fmul.s
  llvm/test/MC/RISCV/rvv/fmv.s
  llvm/test/MC/RISCV/rvv/fothers.s
  llvm/test/MC/RISCV/rvv/freduction.s
  llvm/test/MC/RISCV/rvv/fsub.s
  llvm/test/MC/RISCV/rvv/invalid.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/macc.s
  llvm/test/MC/RISCV/rvv/mask.s
  llvm/test/MC/RISCV/rvv/minmax.s
  llvm/test/MC/RISCV/rvv/mul.s
  llvm/test/MC/RISCV/rvv/mv.s
  llvm/test/MC/RISCV/rvv/or.s
  llvm/test/MC/RISCV/rvv/others.s
  llvm/test/MC/RISCV/rvv/reduction.s
  llvm/test/MC/RISCV/rvv/shift.s
  llvm/test/MC/RISCV/rvv/sign-injection.s
  llvm/test/MC/RISCV/rvv/snippet.s
  llvm/test/MC/RISCV/rvv/store.s
  llvm/test/MC/RISCV/rvv/sub.s
  llvm/test/MC/RISCV/rvv/vsetvl.s
  llvm/test/MC/RISCV/rvv/xor.s

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