[PATCH] D78252: [AArch64] FMLA/FMLS patterns improvement.

[Pavel Iliin via Phabricator via cfe-commits]

ilinpv marked an inline comment as not done.
ilinpv added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8055
 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
+  let Predicates = [HasNEON, HasFullFP16] in {
+  // 1 variant for the .8h version: DUPLANE from 128-bit
----------------
dmgreen wrote:
> ilinpv wrote:
> > dmgreen wrote:
> > > Should we have equal patterns to those below for f32 as well? So using DUP, D vector (4xf16) and possibly from a vector_extract too.
> > I'm worried about performance impact of change fmadd/sub -> fmla/ls in last pattern case.
> What performance impact are you worried about?
I mean, can fmla/ls take more cycles that fmadd/sub, is it any performance improvement of such replacement?


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8077
+
+  def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
+                         (vector_extract (v8f16 V128:$Rm), VectorIndexS:$idx))),
----------------
dmgreen wrote:
> Do you mean the v4f16 variant of this pattern?
This pattern exactly replaces fmadd/sub to fmla/ls, so it is questionable weather or not this pattern is useful.
v4f16 vector_extract variant has no any test cases at all.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78252/new/

https://reviews.llvm.org/D78252