[clang] 6ae3eff - [ARM,CDE] Implement CDE vreinterpret intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-20T14:01:57Z
New Revision: 6ae3eff8baaca95752b1ec9732c605b3d4e8d630

URL: https://github.com/llvm/llvm-project/commit/6ae3eff8baaca95752b1ec9732c605b3d4e8d630
DIFF: https://github.com/llvm/llvm-project/commit/6ae3eff8baaca95752b1ec9732c605b3d4e8d630.diff

LOG: [ARM,CDE] Implement CDE vreinterpret intrinsics

Summary:
This patch implements the following CDE intrinsics:

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);
  uint16x8_t __arm_vreinterpretq_u16_u8 (uint8x16_t in);
  int16x8_t __arm_vreinterpretq_s16_u8 (uint8x16_t in);
  uint32x4_t __arm_vreinterpretq_u32_u8 (uint8x16_t in);
  int32x4_t __arm_vreinterpretq_s32_u8 (uint8x16_t in);
  uint64x2_t __arm_vreinterpretq_u64_u8 (uint8x16_t in);
  int64x2_t __arm_vreinterpretq_s64_u8 (uint8x16_t in);
  float16x8_t __arm_vreinterpretq_f16_u8 (uint8x16_t in);
  float32x4_t __arm_vreinterpretq_f32_u8 (uint8x16_t in);

These intrinsics are header-only because they reuse the existing
MVE vreinterpret clang built-ins.

This set is slightly different from the published specification
(see https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf):
it includes

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);

which was unintentionally ommitted from the spec, and
does not include

  float64x2_t __arm_vreinterpretq_f64_u8 (uint8x16_t in);

The float64x2_t type requires additional implementation
effort, and we are not including it yet.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76300

Added: 
    clang/test/CodeGen/arm-cde-reinterpret.c

Modified: 
    clang/include/clang/Basic/arm_cde.td

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Basic/arm_cde.td b/clang/include/clang/Basic/arm_cde.td
index 2d48cbf21d8c..e258bf5ee83e 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -188,3 +188,11 @@ def vcx3qa : FunctionMacro<
   ["cp", "acc", "n", "m", "imm"],
   "__arm_vcx3qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), "
                      "__arm_vreinterpretq_u8(m), (imm))">;
+
+// vreinterpretq intrinsics required by the ACLE CDE specification
+
+foreach desttype = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32] in {
+  let params = [u8], headerOnly = 1, pnt = PNT_None in
+  def "vreinterpretq_" # desttype : Intrinsic<
+    VecOf<desttype>, (args Vector:$x), (vreinterpret $x, VecOf<desttype>)>;
+}

diff  --git a/clang/test/CodeGen/arm-cde-reinterpret.c b/clang/test/CodeGen/arm-cde-reinterpret.c
new file mode 100644
index 000000000000..569b51bdfdbe
--- /dev/null
+++ b/clang/test/CodeGen/arm-cde-reinterpret.c
@@ -0,0 +1,78 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \
+// RUN:   -target-feature +cdecp0 -target-feature +mve.fp \
+// RUN:   -mfloat-abi hard -O0 -disable-O0-optnone \
+// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include <arm_cde.h>
+
+// CHECK-LABEL: @test_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    ret <16 x i8> [[X:%.*]]
+//
+int8x16_t test_s8(uint8x16_t x) {
+  return __arm_vreinterpretq_s8_u8(x);
+}
+
+// CHECK-LABEL: @test_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16>
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+uint16x8_t test_u16(uint8x16_t x) {
+  return __arm_vreinterpretq_u16_u8(x);
+}
+
+// CHECK-LABEL: @test_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_s32(uint8x16_t x) {
+  return __arm_vreinterpretq_s32_u8(x);
+}
+
+// CHECK-LABEL: @test_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_u32(uint8x16_t x) {
+  return __arm_vreinterpretq_u32_u8(x);
+}
+
+// CHECK-LABEL: @test_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-NEXT:    ret <2 x i64> [[TMP0]]
+//
+int64x2_t test_s64(uint8x16_t x) {
+  return __arm_vreinterpretq_s64_u8(x);
+}
+
+// CHECK-LABEL: @test_u64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-NEXT:    ret <2 x i64> [[TMP0]]
+//
+uint64x2_t test_u64(uint8x16_t x) {
+  return __arm_vreinterpretq_u64_u8(x);
+}
+
+// CHECK-LABEL: @test_f16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half>
+// CHECK-NEXT:    ret <8 x half> [[TMP0]]
+//
+float16x8_t test_f16(uint8x16_t x) {
+  return __arm_vreinterpretq_f16_u8(x);
+}
+
+// CHECK-LABEL: @test_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float>
+// CHECK-NEXT:    ret <4 x float> [[TMP0]]
+//
+float32x4_t test_f32(uint8x16_t x) {
+  return __arm_vreinterpretq_f32_u8(x);
+}