[PATCH] D76238: [SveEmitter] Implement builtins for contiguous loads/stores
Sjoerd Meijer via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Mar 19 03:44:58 PDT 2020
SjoerdMeijer added a comment.
Some nits inlined
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Comment at: clang/include/clang/Basic/AArch64SVETypeFlags.h:72
+ bool isStructStore() const { return Flags & IsStructStore; }
+ bool isZxtReturn() const { return Flags & IsZxtReturn; }
+
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nit: this one is non obvious (at least to me), so perhaps worth a comment what this is. I can guess that Zext means zero extending, but you know, the context...
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Comment at: clang/include/clang/Basic/arm_sve.td:128
def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>;
+def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8>;
+def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZxtReturn], MemEltTyInt8>;
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nit: don't think we have a coding style for tablegen, but it is exceeding 80 characters, even making this on phabricator a bit difficult to read, perhaps you can reshuffle this a bit.
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Comment at: clang/lib/CodeGen/CGBuiltin.cpp:7467
+
+ return IsZxtReturn ? Builder.CreateZExt(Load, VectorTy)
+ : Builder.CreateSExt(Load, VectorTy);
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nit: and now looking at this, this can be a zero or sign extend, so `Zxt` is slightly misleading?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76238/new/
https://reviews.llvm.org/D76238
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