[PATCH] D75169: [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32

[John McCall via Phabricator via cfe-commits]

rjmccall added a comment.

In D75169#1926545 <https://reviews.llvm.org/D75169#1926545>, @pratlucas wrote:

> Hi @rjmccall,
>  I agree those kind of tweaks do not look good. The issue here, though, is that argument coercion currently ignores the target's endian information when performing coercion through memory.
>  This happens for any type that requires memory coercion, so unfortunately using `[1 x i32]` does not do the trick.


Oh, wait, AAPCS wants half values to be passed in the *least* significant bits of a GPR, even on big-endian machines?  That's certainly more convenient, but it's a weird inconsistency with the otherwise iron rule of the calling convention, which that it's exactly as if you laid all of the arguments out in memory and then popped the first four 32-bit values off.  We're talking about a calling convention here that literally skips registers in order to "align" arguments.

Can we not just coerce to i16?  Will LLVM not pass an i16 in the least-significant bits of a register?


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https://reviews.llvm.org/D75169