[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

Thu Feb 27 13:47:13 PST 2020

craig.topper added inline comments.

================
Comment at: clang/lib/Basic/Targets/X86.cpp:1786
+    // i386
+    case CK_i386:
+    // Netburst
----------------
I found the documentation for the 82385 cache controller chip for the 386. It's a bit weird. The tags for the cache are based on 16 byte lines, but there are valid bits for every 2 bytes within that line. So its possible for only a portion of a line to be valid.

================
Comment at: clang/lib/Basic/Targets/X86.cpp:1840
+    // Core
+    case CK_Core2:
+    case CK_Generic:
----------------
If Yonah and Penryn are 64, then Core2 should be as well. It's the generation between them.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74918/new/

https://reviews.llvm.org/D74918