[PATCH] D74918: Add method to TargetInfo to get CPU cache line size
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Feb 20 15:37:33 PST 2020
craig.topper added inline comments.
================
Comment at: clang/lib/Basic/Targets/X86.cpp:1738
+// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
+// | i486 | 64 | "four doublewords" https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf |
----------------
I'd be surprised if 386 is larger than 486 or 586.
================
Comment at: clang/lib/Basic/Targets/X86.cpp:1739
+// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
+// | i486 | 64 | "four doublewords" https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf |
+// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
----------------
doubleword is 32-bits on X86. So 4 double words is 16 bytes I think?
================
Comment at: clang/lib/Basic/Targets/X86.cpp:1833
+ case CK_Cannonlake:
+ case CK_Tigerlake:
+ case CK_Lakemont:
----------------
Nehalem, coooperlake, cannonlake and tigerlake are all 64.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74918/new/
https://reviews.llvm.org/D74918
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