[PATCH] D74918: Add method to TargetInfo to get CPU cache line size

[James Y Knight via Phabricator via cfe-commits]

jyknight added a comment.

As I've mentioned before, depending on what this will be used for, "64" is not a _useful_ answer if you want to know how your memory accesses will behave on modern intel x86 CPUs, despite being the "correct" answer for cache-line size. But, modern intel CPUs fetch aligned-pairs of cache-lines together.  Therefore, you'll start to see cache interference effects as-if the cache-lines were 128 bytes, rather than 64 bytes. (This may or may not also apply to AMD cpus, I haven't looked into it.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74918/new/

https://reviews.llvm.org/D74918