[PATCH] D72722: [FPEnv] [SystemZ] Platform-specific builtin constrained FP enablement

[Ulrich Weigand via Phabricator via cfe-commits]

uweigand added a comment.

> What are the semantics of vfnmadb with respect to when it rounds vs the negation?

Hmm, interesting.  The z/Architecture Principles of Operation states:

> The results for each element of VECTOR FP NEGA-
>  TIVE MULTIPLY AND ADD and VECTOR FP NEGA-
>  TIVE MULTIPLY AND SUBTRACT are the same as
>  for VECTOR FP MULTIPLY AND ADD and VECTOR
>  FP MULTIPLY AND SUBTRACT, respectively, except
>  the sign bit of numeric results are inverted. When the
>  result is a NaN it’s sign bit is unchanged.

So as far as rounding is concerned, the vfnmadb should have the exact same result as a vfmadb ; vflcdb sequence we'd get from a fma/fneg.

I hadn't realized the NaN special treatment before.  This makes the result actually different in that case.  OTOH I guess IEEE only says the result has to some NaN, not particularly **which** NaN, so that's probably also OK.  (In any case it's unrelated to strict FP.)


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https://reviews.llvm.org/D72722