[PATCH] D72218: [clang-tidy] new altera kernel name restriction check

[Frank Derry Wanye via Phabricator via cfe-commits]

ffrankies created this revision.
ffrankies added reviewers: alexfh, hokein, aaron.ballman.
ffrankies added projects: clang-tools-extra, clang, LLVM.
Herald added subscribers: mgehre, ormris, arphaman, xazax.hun, Anastasia, mgorny.

This lint check is part of the FLOCL (FPGA Linters for OpenCL) project out of the Synergy Lab at Virginia Tech.

FLOCL is a set of lint checks aimed at FPGA developers who code in OpenCL.

The altera kernel name restriction check finds kernel files and include directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl". Such kernel file names cause the Altera Offline Compiler to generate intermediate design files that have the same names as certain internal files, which leads to a compilation error.

As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA SDK for OpenCL Pro Edition: Programming Guide."


Repository:
  rCTE Clang Tools Extra

https://reviews.llvm.org/D72218

Files:
  clang-tidy/CMakeLists.txt
  clang-tidy/ClangTidyForceLinker.h
  clang-tidy/altera/AlteraTidyModule.cpp
  clang-tidy/altera/CMakeLists.txt
  clang-tidy/altera/KernelNameRestrictionCheck.cpp
  clang-tidy/altera/KernelNameRestrictionCheck.h
  docs/ReleaseNotes.rst
  docs/clang-tidy/checks/altera-kernel-name-restriction.rst
  docs/clang-tidy/checks/list.rst
  docs/clang-tidy/index.rst
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/KERNEL.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/VHDL.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/Verilog.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/kernel.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/kernel.h
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/other_Verilog.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/otherdir/vhdl.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/otherthing.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some/dir/kernel.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/some_kernel.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/somedir/verilog.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/thing.h
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vERILOG.cl
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/verilog.h
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl.CL
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl.h
  test/clang-tidy/checkers/Inputs/altera-kernel-name-restriction/vhdl_number_two.cl
  test/clang-tidy/checkers/altera-kernel-name-restriction.cpp

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