[PATCH] D70948: [ARM][MVE][Intrinsics] Add VMULH/VRMULH intrinsics.

[Dave Green via Phabricator via cfe-commits]

dmgreen added a comment.

Looks good to me, with a couple of minor nitpicks (that I'm not sure matter or not).



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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:3626
 
-class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size,
+class MVE_VxMULH<string iname, string suffix, bits<2> size, bit U,
                  bit round, list<dag> pattern=[]>
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Any strong reason to switch these around? From what I can tell most of the patterns are (suffix, unsigned, size) in that order. Although that doesn't seem to be universal. Might as well try to keep it consistent, if you do not have a reason to swap them.


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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:3644
+multiclass MVE_VxMULH_m<string iname, MVEVectorVTInfo VTI,
+                      SDNode unpred_op, Intrinsic pred_int,
+                      bit round> {
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Formatting.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70948/new/

https://reviews.llvm.org/D70948