[clang] db73bcd - ARM-NEON: separate soon-to-be conflicting f16 patterns. NFC.

[Tim Northover via cfe-commits]

Author: Tim Northover
Date: 2019-11-20T13:20:02Z
New Revision: db73bcd98ef4ffbe91405a5adfcfdcd83bc007f4

URL: https://github.com/llvm/llvm-project/commit/db73bcd98ef4ffbe91405a5adfcfdcd83bc007f4
DIFF: https://github.com/llvm/llvm-project/commit/db73bcd98ef4ffbe91405a5adfcfdcd83bc007f4.diff

LOG: ARM-NEON: separate soon-to-be conflicting f16 patterns. NFC.

This separates some intrinsic definitions into multiple instantiations because
they use a modifier that forces the float size to a given value. That modifier
won't work in the new NeonEmitter modifier scheme and committing this
separately allows the Python script to be run on the .td files to perform the
conversion automatically.

Added: 
    

Modified: 
    clang/include/clang/Basic/arm_fp16.td

Removed: 
    


################################################################################
diff  --git a/clang/include/clang/Basic/arm_fp16.td b/clang/include/clang/Basic/arm_fp16.td
index ca33a8d2ec0b..bb9873efac85 100644
--- a/clang/include/clang/Basic/arm_fp16.td
+++ b/clang/include/clang/Basic/arm_fp16.td
@@ -43,7 +43,9 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarc
   def FRINTX_S64H     : SInst<"vrndx", "ss", "Sh">;
 
   // Conversion
-  def SCALAR_SCVTFSH  : SInst<"vcvth_f16", "Ys", "silUsUiUl">;
+  def SCALAR_SCVTFSH  : SInst<"vcvth_f16", "Ys", "sUs">;
+  def SCALAR_SCVTFSH1 : SInst<"vcvth_f16", "Ys", "iUi">;
+  def SCALAR_SCVTFSH2 : SInst<"vcvth_f16", "Ys", "lUl">;
   def SCALAR_FCVTZSH  : SInst<"vcvt_s16", "$s", "Sh">;
   def SCALAR_FCVTZSH1 : SInst<"vcvt_s32", "Is", "Sh">;
   def SCALAR_FCVTZSH2 : SInst<"vcvt_s64", "Ls", "Sh">;
@@ -75,7 +77,9 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarc
   def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "Us", "Sh">;
   def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "Os", "Sh">;
   let isVCVT_N = 1 in {
-    def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">;
+    def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "sUs">;
+    def SCALAR_SCVTFSH1O: SInst<"vcvth_n_f16", "Ysi", "iUi">;
+    def SCALAR_SCVTFSH2O: SInst<"vcvth_n_f16", "Ysi", "lUl">;
     def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">;
     def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">;
     def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">;