[PATCH] D70297: [ARM,MVE] Add intrinsics for vector comparisons.

Simon Tatham via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Fri Nov 15 02:04:46 PST 2019


simon_tatham created this revision.
simon_tatham added reviewers: ostannard, MarkMurrayARM, dmgreen.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls.
Herald added projects: clang, LLVM.

This adds the `vcmp` family of ACLE MVE intrinsics: vector/vector,
vector/scalar, and the predicated forms of both. All are represented
using standard existing IR: vector/scalar comparisons are represented
by making a vector out of the scalar first, and predicated forms are
represented by taking the bitwise AND of the input predicate and the
output of the comparison. Existing LLVM-side tests demonstrate that
ISel will pattern-match all of that back down to single MVE VCMPs.

The idiom of handling a vector/scalar operation by generating IR to
expand the scalar into a second vector is going to be needed for a lot
of MVE intrinsics. Since LLVM IR doesn't have a single operation to do
that expansion, I've written a helper function to do it conveniently,
and a Tablegen node that will make it easy to reuse in all the future
operations that have to do the same job.

The comparison intrinsics are the first ones that have to //return// a
predicate, in the user-facing `mve_pred16_t` format. This means we
have to use the `arm_mve_pred_v2i` low-level intrinsic to convert it
back from the logical `<n x i1>` form used in IR. But that means that
if you pass the result of a vcmp as input to a predicated intrinsic,
e.g.

  mve_pred16_t pred = vcmpeqq(v1, v2);
  v_out = vaddq_m(v_inactive, v3, v4, pred);

then you need to avoid the generated code moving the predicate out of
`p0` and back into it again. So I've added InstCombine rules to remove
round trips of the form `v2i(i2v(x))` and `i2v(v2i(x))` (and dealt
with the known/demanded bits while I was there), and as a result, you
get just the generated code you wanted:

  vpt.u16 eq, q1, q2
  vaddt.u16 q0, q3, q4


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70297

Files:
  clang/include/clang/Basic/arm_mve.td
  clang/include/clang/Basic/arm_mve_defs.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/arm-mve-intrinsics/compare.c
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/test/CodeGen/Thumb2/mve-vpt-from-intrinsics.ll
  llvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll

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