[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

[Luís Marques via Phabricator via cfe-commits]

luismarques requested changes to this revision.
luismarques added inline comments.
This revision now requires changes to proceed.


================
Comment at: libunwind/include/__libunwind_config.h:26
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC     31
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV     63
 
----------------
The highest dwarf register number is 64, the Alternate Frame Return Column. See https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers-


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68362/new/

https://reviews.llvm.org/D68362