[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

[Simon Cook via Phabricator via cfe-commits]

simoncook created this revision.
simoncook added reviewers: asb, lenary.
Herald added subscribers: llvm-commits, cfe-commits, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar, hiraditya, kristof.beyls, javed.absar.
Herald added projects: clang, LLVM.

This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. It is possible to reserve registers that the compiler
later ignores (such as x2/sp); this matches GCC's behavior.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67185

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-fixed-x-register.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/reserved-regs.ll

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