[PATCH] D66822: Hardware cache line size builtins

[JF Bastien via Phabricator via cfe-commits]

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Sorry for the delayed response, I was on vacation. Thanks for tackling it!

I don't think this is the approach I would take. From my dev meeting lightning talk I would instead:

1. Add to target infrastructure
2. Overriding in sub-targets using `-march` or `-mcpu`
3. Overriding on the command line
4. If set in target, expose the builtin
5. Generic le32 / be32 ARM targets expose constructive / destructive as 64B
6. Generic le64 / be64 ARM targets expose constructive as 64B and destructive as 128B
7. Generic x86 expose constructive / destructive as 64B
8. Honor existing sub-target preferences
9. Let maintainers of other targets choose appropriate size

I think this needs to be split up into a few patches, at least one per target. libc++ would then only expose the feature if `__has_builtin` is true. I'm happy to go into more details if what I say above is to vague :)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D66822/new/

https://reviews.llvm.org/D66822