[PATCH] D66524: [SVE][Inline-Asm] Add constraints for SVE predicate registers

[Kerry McLaughlin via Phabricator via cfe-commits]

kmclaughlin created this revision.
kmclaughlin added reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened.
Herald added subscribers: psnobl, rkruppe, tschuett, javed.absar.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
kmclaughlin added a parent revision: D66302: [SVE][Inline-Asm] Support for SVE asm operands.

Adds the following inline asm constraints for SVE:

- Upl: One of the low eight SVE predicate registers, P0 to P7 <https://reviews.llvm.org/P7> inclusive
- Upa: SVE predicate register with full range, P0 to P15 <https://reviews.llvm.org/P15>


Repository:
  rL LLVM

https://reviews.llvm.org/D66524

Files:
  docs/LangRef.rst
  lib/IR/InlineAsm.cpp
  lib/Target/AArch64/AArch64AsmPrinter.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  test/CodeGen/AArch64/aarch64-sve-asm.ll

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