[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL369093: [RISCV] Add inline asm constraint A for RISC-V (authored by lewis-revill, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54295?vs=215414&id=215556#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.cpp
  cfe/trunk/test/CodeGen/riscv-inline-asm.c


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===================================================================
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 
Index: cfe/trunk/test/CodeGen/riscv-inline-asm.c
===================================================================
--- cfe/trunk/test/CodeGen/riscv-inline-asm.c
+++ cfe/trunk/test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}


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