[PATCH] D63417: [RISCV] Specify registers used for exception handling

[Edward Jones via Phabricator via cfe-commits]

edward-jones updated this revision to Diff 205542.
edward-jones retitled this revision from "[WIP][RISCV] Specify registers used for exception handling" to "[RISCV] Specify registers used for exception handling".
edward-jones edited the summary of this revision.
edward-jones added a comment.

Added tests


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63417/new/

https://reviews.llvm.org/D63417

Files:
  lib/Basic/Targets/RISCV.h
  test/CodeGen/builtin-riscv.c


Index: test/CodeGen/builtin-riscv.c
===================================================================
--- /dev/null
+++ test/CodeGen/builtin-riscv.c
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -Wall -Werror -triple riscv32 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+void test_eh_return_data_regno()
+{
+  // CHECK: store volatile i32 10
+  // CHECK: store volatile i32 11
+  volatile int res;
+  res = __builtin_eh_return_data_regno(0);
+  res = __builtin_eh_return_data_regno(1);
+}
Index: lib/Basic/Targets/RISCV.h
===================================================================
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -57,6 +57,15 @@
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
+  int getEHDataRegisterNumber(unsigned RegNo) const override {
+    if (RegNo == 0)
+      return 10;
+    else if (RegNo == 1)
+      return 11;
+    else
+      return -1;
+  }
+
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,


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