r362129 - Reapply: LLVM IR: update Clang tests for byval being a typed attribute.
Tim Northover via cfe-commits
cfe-commits at lists.llvm.org
Thu May 30 11:49:19 PDT 2019
Author: tnorthover
Date: Thu May 30 11:49:19 2019
New Revision: 362129
URL: http://llvm.org/viewvc/llvm-project?rev=362129&view=rev
Log:
Reapply: LLVM IR: update Clang tests for byval being a typed attribute.
Since byval is now a typed attribute it gets sorted slightly differently by
LLVM when the order of attributes is being canonicalized. This updates the few
Clang tests that depend on the old order.
Clang patch is unchanged.
Modified:
cfe/trunk/test/CodeGen/aapcs-align.cpp
cfe/trunk/test/CodeGenCXX/builtin-source-location.cpp
cfe/trunk/test/CodeGenCXX/wasm-args-returns.cpp
cfe/trunk/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
cfe/trunk/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
cfe/trunk/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
Modified: cfe/trunk/test/CodeGen/aapcs-align.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aapcs-align.cpp?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/aapcs-align.cpp (original)
+++ cfe/trunk/test/CodeGen/aapcs-align.cpp Thu May 30 11:49:19 2019
@@ -95,8 +95,8 @@ void g4() {
f4m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g4
-// CHECK: call void @f4(i32 1, %struct.SF16* byval nonnull align 8
-// CHECK: call void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, %struct.SF16* byval nonnull align 8
+// CHECK: call void @f4(i32 1, %struct.SF16* nonnull byval align 8
+// CHECK: call void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, %struct.SF16* nonnull byval align 8
// CHECK: declare void @f4(i32, %struct.SF16* byval align 8)
// CHECK: declare void @f4m(i32, i32, i32, i32, i32, %struct.SF16* byval align 8)
Modified: cfe/trunk/test/CodeGenCXX/builtin-source-location.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/builtin-source-location.cpp?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenCXX/builtin-source-location.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/builtin-source-location.cpp Thu May 30 11:49:19 2019
@@ -104,7 +104,7 @@ struct TestInit {
//
// CHECK-CTOR-GLOBAL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret %[[TMP_ONE:[^,]*]],
// CHECK-CTOR-GLOBAL-SAME: i32 3400, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]],
-// CHECK-CTOR-GLOBAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* @GlobalInitVal, %struct.source_location* {{[^%]*}}%[[TMP_ONE]])
+// CHECK-CTOR-GLOBAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* @GlobalInitVal, %struct.source_location* {{.*}}%[[TMP_ONE]])
#line 3400 "GlobalInitVal.cpp"
TestInit GlobalInitVal;
@@ -119,7 +119,7 @@ extern "C" void test_init_function() {
//
// CHECK-CTOR-LOCAL: call void @_ZN15source_location7currentEjjPKcS1_(%struct.source_location* sret %[[TMP:[^,]*]],
// CHECK-CTOR-LOCAL-SAME: i32 3500, i32 {{[0-9]+}}, {{[^@]*}}@[[FILE]], {{[^@]*}}@[[FUNC]],
-// CHECK-CTOR-LOCAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* %init_local, %struct.source_location* {{[^%]*}}%[[TMP]])
+// CHECK-CTOR-LOCAL-NEXT: call void @_ZN8TestInitC1E15source_location(%struct.TestInit* %init_local, %struct.source_location* {{.*}}%[[TMP]])
#line 3500 "LocalInitVal.cpp"
TestInit init_local;
sink(init_local);
Modified: cfe/trunk/test/CodeGenCXX/wasm-args-returns.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/wasm-args-returns.cpp?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenCXX/wasm-args-returns.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/wasm-args-returns.cpp Thu May 30 11:49:19 2019
@@ -30,12 +30,12 @@ struct two_fields {
double d, e;
};
test(two_fields);
-// CHECK: define void @_Z7forward10two_fields(%struct.two_fields* noalias nocapture sret %{{.*}}, %struct.two_fields* byval nocapture readonly align 8 %{{.*}})
+// CHECK: define void @_Z7forward10two_fields(%struct.two_fields* noalias nocapture sret %{{.*}}, %struct.two_fields* nocapture readonly byval align 8 %{{.*}})
//
// CHECK: define void @_Z15test_two_fieldsv()
// CHECK: %[[tmp:.*]] = alloca %struct.two_fields, align 8
// CHECK: call void @_Z14def_two_fieldsv(%struct.two_fields* nonnull sret %[[tmp]])
-// CHECK: call void @_Z3use10two_fields(%struct.two_fields* byval nonnull align 8 %[[tmp]])
+// CHECK: call void @_Z3use10two_fields(%struct.two_fields* nonnull byval align 8 %[[tmp]])
// CHECK: ret void
//
// CHECK: declare void @_Z3use10two_fields(%struct.two_fields* byval align 8)
Modified: cfe/trunk/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp Thu May 30 11:49:19 2019
@@ -20,7 +20,7 @@ void f_struct_with_mdp(struct_with_mdp a
struct struct_with_mdp_too_much {
char *a; char *b; char *c; char *d; test_struct_mdp e;
};
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mdp_too_much{{.*}}({{.*}} byval {{.*}} %a)
+// CHECK-LABEL: define void @{{.*}}f_struct_with_mdp_too_much{{.*}}({{.*}} byval
void f_struct_with_mdp_too_much(struct_with_mdp_too_much a) {
(void)a;
}
Modified: cfe/trunk/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl Thu May 30 11:49:19 2019
@@ -309,7 +309,7 @@ void func_single_struct_element_struct_a
// CHECK: void @func_different_size_type_pair_arg(i64 %arg1.coerce0, i32 %arg1.coerce1)
void func_different_size_type_pair_arg(different_size_type_pair arg1) { }
-// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* byval nocapture align 4 %arg)
+// CHECK: void @func_flexible_array_arg(%struct.flexible_array addrspace(5)* nocapture byval align 4 %arg)
void func_flexible_array_arg(flexible_array arg) { }
// CHECK: define float @func_f32_ret()
@@ -450,11 +450,11 @@ flexible_array func_flexible_array_ret()
// CHECK: define void @func_reg_state_lo(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %s.coerce0, float %s.coerce1, i32 %s.coerce2)
void func_reg_state_lo(int4 arg0, int4 arg1, int4 arg2, int arg3, struct_arg_t s) { }
-// CHECK: define void @func_reg_state_hi(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %arg4, %struct.struct_arg addrspace(5)* byval nocapture align 4 %s)
+// CHECK: define void @func_reg_state_hi(<4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, i32 %arg3, i32 %arg4, %struct.struct_arg addrspace(5)* nocapture byval align 4 %s)
void func_reg_state_hi(int4 arg0, int4 arg1, int4 arg2, int arg3, int arg4, struct_arg_t s) { }
// XXX - Why don't the inner structs flatten?
-// CHECK: define void @func_reg_state_num_regs_nested_struct(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* byval nocapture align 8 %arg4)
+// CHECK: define void @func_reg_state_num_regs_nested_struct(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.nested %arg2.coerce1, i32 %arg3.coerce0, %struct.nested %arg3.coerce1, %struct.num_regs_nested_struct addrspace(5)* nocapture byval align 8 %arg4)
void func_reg_state_num_regs_nested_struct(int4 arg0, int arg1, num_regs_nested_struct arg2, num_regs_nested_struct arg3, num_regs_nested_struct arg4) { }
// CHECK: define void @func_double_nested_struct_arg(<4 x i32> %arg0, i32 %arg1, i32 %arg2.coerce0, %struct.double_nested %arg2.coerce1, i16 %arg2.coerce2)
@@ -469,7 +469,7 @@ double_nested_struct func_double_nested_
// CHECK: define void @func_large_struct_padding_arg_direct(i8 %arg.coerce0, i32 %arg.coerce1, i8 %arg.coerce2, i32 %arg.coerce3, i8 %arg.coerce4, i8 %arg.coerce5, i16 %arg.coerce6, i16 %arg.coerce7, [3 x i8] %arg.coerce8, i64 %arg.coerce9, i32 %arg.coerce10, i8 %arg.coerce11, i32 %arg.coerce12, i16 %arg.coerce13, i8 %arg.coerce14)
void func_large_struct_padding_arg_direct(large_struct_padding arg) { }
-// CHECK: define void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture %out, %struct.large_struct_padding addrspace(5)* byval nocapture readonly align 8 %arg)
+// CHECK: define void @func_large_struct_padding_arg_store(%struct.large_struct_padding addrspace(1)* nocapture %out, %struct.large_struct_padding addrspace(5)* nocapture readonly byval align 8 %arg)
void func_large_struct_padding_arg_store(global large_struct_padding* out, large_struct_padding arg) {
*out = arg;
}
@@ -487,7 +487,7 @@ void v3i32_pair_reg_count(int3_pair *arg
void v4i16_reg_count(short4 arg0, short4 arg1, short4 arg2, short4 arg3,
short4 arg4, short4 arg5, struct_4regs arg6) { }
-// CHECK: define void @v4i16_pair_reg_count_over(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, <4 x i16> %arg6, %struct.struct_4regs addrspace(5)* byval nocapture align 4 %arg7)
+// CHECK: define void @v4i16_pair_reg_count_over(<4 x i16> %arg0, <4 x i16> %arg1, <4 x i16> %arg2, <4 x i16> %arg3, <4 x i16> %arg4, <4 x i16> %arg5, <4 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval align 4 %arg7)
void v4i16_pair_reg_count_over(short4 arg0, short4 arg1, short4 arg2, short4 arg3,
short4 arg4, short4 arg5, short4 arg6, struct_4regs arg7) { }
@@ -495,7 +495,7 @@ void v4i16_pair_reg_count_over(short4 ar
void v3i16_reg_count(short3 arg0, short3 arg1, short3 arg2, short3 arg3,
short3 arg4, short3 arg5, struct_4regs arg6) { }
-// CHECK: define void @v3i16_reg_count_over(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, <3 x i16> %arg6, %struct.struct_4regs addrspace(5)* byval nocapture align 4 %arg7)
+// CHECK: define void @v3i16_reg_count_over(<3 x i16> %arg0, <3 x i16> %arg1, <3 x i16> %arg2, <3 x i16> %arg3, <3 x i16> %arg4, <3 x i16> %arg5, <3 x i16> %arg6, %struct.struct_4regs addrspace(5)* nocapture byval align 4 %arg7)
void v3i16_reg_count_over(short3 arg0, short3 arg1, short3 arg2, short3 arg3,
short3 arg4, short3 arg5, short3 arg6, struct_4regs arg7) { }
@@ -505,7 +505,7 @@ void v2i16_reg_count(short2 arg0, short2
short2 arg8, short2 arg9, short2 arg10, short2 arg11,
struct_4regs arg13) { }
-// CHECK: define void @v2i16_reg_count_over(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, <2 x i16> %arg12, %struct.struct_4regs addrspace(5)* byval nocapture align 4 %arg13)
+// CHECK: define void @v2i16_reg_count_over(<2 x i16> %arg0, <2 x i16> %arg1, <2 x i16> %arg2, <2 x i16> %arg3, <2 x i16> %arg4, <2 x i16> %arg5, <2 x i16> %arg6, <2 x i16> %arg7, <2 x i16> %arg8, <2 x i16> %arg9, <2 x i16> %arg10, <2 x i16> %arg11, <2 x i16> %arg12, %struct.struct_4regs addrspace(5)* nocapture byval align 4 %arg13)
void v2i16_reg_count_over(short2 arg0, short2 arg1, short2 arg2, short2 arg3,
short2 arg4, short2 arg5, short2 arg6, short2 arg7,
short2 arg8, short2 arg9, short2 arg10, short2 arg11,
@@ -515,7 +515,7 @@ void v2i16_reg_count_over(short2 arg0, s
void v2i8_reg_count(char2 arg0, char2 arg1, char2 arg2, char2 arg3,
char2 arg4, char2 arg5, struct_4regs arg6) { }
-// CHECK: define void @v2i8_reg_count_over(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6, %struct.struct_4regs addrspace(5)* byval nocapture align 4 %arg7)
+// CHECK: define void @v2i8_reg_count_over(<2 x i8> %arg0, <2 x i8> %arg1, <2 x i8> %arg2, <2 x i8> %arg3, <2 x i8> %arg4, <2 x i8> %arg5, i32 %arg6, %struct.struct_4regs addrspace(5)* nocapture byval align 4 %arg7)
void v2i8_reg_count_over(char2 arg0, char2 arg1, char2 arg2, char2 arg3,
char2 arg4, char2 arg5, int arg6, struct_4regs arg7) { }
Modified: cfe/trunk/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl
URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl?rev=362129&r1=362128&r2=362129&view=diff
==============================================================================
--- cfe/trunk/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/kernels-have-spir-cc-by-default.cl Thu May 30 11:49:19 2019
@@ -27,7 +27,7 @@ typedef struct test_struct {
kernel void test_single(int_single input, global int* output) {
// CHECK: spir_kernel
// AMDGCN: define amdgpu_kernel void @test_single
-// CHECK: struct.int_single* byval nocapture
+// CHECK: struct.int_single* nocapture {{.*}} byval
// CHECK: i32* nocapture %output
output[0] = input.a;
}
@@ -35,7 +35,7 @@ kernel void test_single(int_single input
kernel void test_pair(int_pair input, global int* output) {
// CHECK: spir_kernel
// AMDGCN: define amdgpu_kernel void @test_pair
-// CHECK: struct.int_pair* byval nocapture
+// CHECK: struct.int_pair* nocapture {{.*}} byval
// CHECK: i32* nocapture %output
output[0] = (int)input.a;
output[1] = (int)input.b;
@@ -44,7 +44,7 @@ kernel void test_pair(int_pair input, gl
kernel void test_kernel(test_struct input, global int* output) {
// CHECK: spir_kernel
// AMDGCN: define amdgpu_kernel void @test_kernel
-// CHECK: struct.test_struct* byval nocapture
+// CHECK: struct.test_struct* nocapture {{.*}} byval
// CHECK: i32* nocapture %output
output[0] = input.elementA;
output[1] = input.elementB;
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