[PATCH] D60272: [Aarch64] Add v8.2-a half precision element extract intrinsics

[Diogo N. Sampaio via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL358276: [Aarch64] Add v8.2-a half precision element extract intrinsics (authored by dnsampaio, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60272/new/

https://reviews.llvm.org/D60272

Files:
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c


Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -7847,6 +7847,14 @@
                           : Intrinsic::aarch64_neon_sqsub;
     return EmitNeonCall(CGM.getIntrinsic(AccInt, Int64Ty), Ops, "vqdmlXl");
   }
+  case NEON::BI__builtin_neon_vduph_lane_f16: {
+    return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
+                                        "vget_lane");
+  }
+  case NEON::BI__builtin_neon_vduph_laneq_f16: {
+    return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
+                                        "vgetq_lane");
+  }
   }
 
   llvm::VectorType *VTy = GetNeonType(this, Type);
Index: cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
===================================================================
--- cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
+++ cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
@@ -1618,3 +1618,16 @@
   return vtrn2q_f16(a, b);
 }
 
+// CHECK-LABEL: @test_vduph_laneq_f16(
+// CHECK:        [[V:%.*]] = extractelement <8 x half> [[V2:%.*]], i32 7
+// CHECK-NEXT:   ret half [[V]]
+float16_t test_vduph_laneq_f16(float16x8_t vec) {
+  return vduph_laneq_f16(vec, 7);
+}
+
+// CHECK-LABEL: @test_vduph_lane_f16(
+// CHECK:        [[V:%.*]] = extractelement <4 x half> [[V2:%.*]], i32 3
+// CHECK-NEXT:   ret half [[V]]
+float16_t test_vduph_lane_f16(float16x4_t vec) {
+  return vduph_lane_f16(vec, 3);
+}


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