[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V
Lewis Revill via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue Feb 19 02:55:51 PST 2019
lewis-revill updated this revision to Diff 187335.
lewis-revill added a comment.
Herald added subscribers: llvm-commits, jdoerfert.
Herald added a project: LLVM.
Correct test.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D54295/new/
https://reviews.llvm.org/D54295
Files:
lib/Basic/Targets/RISCV.cpp
test/CodeGen/riscv-inline-asm.c
Index: test/CodeGen/riscv-inline-asm.c
===================================================================
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
// CHECK: call void asm sideeffect "", "K"(i32 0)
asm volatile ("" :: "K"(0));
}
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+ asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===================================================================
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
// A 5-bit unsigned immediate for CSR access instructions.
Info.setRequiresImmediate(0, 31);
return true;
+ case 'A':
+ // An address that is held in a general-purpose register.
+ Info.setAllowsMemory();
+ return true;
}
}
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