[PATCH] D49754: Add -m(no-)spe, and e500 CPU definitions and support to clang

vit9696 via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Mon Feb 18 06:58:35 PST 2019


vit9696 added a comment.

@jhibbits, @kthomsen, it appears that current patchset has issues when handling && on me. I have it applied over llvm 8.0.0 rc2, and the following code returns 0 to me with -O2 and below:

  #include <stdio.h>
  
  #define FEQUAL(x,y) (((x) - (y)) < 0.000001) // could put fabs if needed
  
  typedef struct {
    float x;
    float y;
  } float2;
  
  static bool __attribute__((noinline)) equals(float2* f40, float2* f41) {
      return FEQUAL(f40->x, f41->x) && FEQUAL(f40->y, f41->y);
  }
  
  int main() {
      float2 a = {0.721569, 0.1234};
      float2 b = {0.721569, 0.1234};
  
      printf("%d\n", equals(&a, &b));
  }

Does it reproduce for you?

GCC output (working):

  # _Bool __fastcall equals(float2 *f40, float2 *f41)
  .globl equals
  equals:
    lwz       r9, 0(r3)
    lis       r10, -0x7FFF
    lwz       r8, 0(r4)
    addi      r10, r10, -0x7198 # 0x80008E68
    evldd     r10, 0(r10)
    efssub    r9, r9, r8
    efdcfs    r9, r9
    efdcmplt  cr7, r9, r10
    ble       cr7, loc_80000048
    lwz       r3, 4(r3)
    lwz       r9, 4(r4)
    efssub    r3, r3, r9
    efdcfs    r3, r3
    efdcmplt  cr7, r3, r10
    mfcr      r3
    extrwi    r3, r3, 1,29
    clrlwi    r3, r3, 24
    blr
  loc_80000048:
    li        r3, 0
    blr

LLVM output (not working):

  # _Bool __fastcall equals(float2 *f40, float2 *f41)
  .globl equals
  equals:
    lwz       r6, 0(r3)
    lwz       r7, 0(r4)
    li        r5, -0x6160
    lis       r8, -0x7FFF
    evlddx    r5, r8, r5
    efssub    r6, r6, r7
    efdcfs    r6, r6
    efdcmplt  cr0, r6, r5
    bge       loc_800002B0
    lwz       r3, 4(r3)
    lwz       r4, 4(r4)
    efssub    r3, r3, r4
    efdcfs    r3, r3
    efdcmplt  cr0, r3, r5
    b         loc_800002B4
  loc_800002B0:
    crclr     gt
  loc_800002B4:
    li        r3, 0
    li        r4, 1
    bgt       loc_800002C4
    blr
  loc_800002C4:
    addi      r3, r4, 0
    blr


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D49754/new/

https://reviews.llvm.org/D49754





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