[PATCH] D35118: [AArch64] Add support for handling the +sve target feature

[Renato Golin via Phabricator via cfe-commits]

rengolin added a comment.

In https://reviews.llvm.org/D35118#807712, @aemerson wrote:

> In https://reviews.llvm.org/D35118#806730, @rengolin wrote:
>
> > @jmolloy Can you check this change, please?
>
>
> I'm not really removing FPUMode, I'm just converting an enum to a bit field. FPUMode, i.e. no NEON, after this change is now represented by simply having all bits be 0. See the equivalent implementation for ARM which does the same thing.


That's not really a bit field, but the point is that you're removing the explicit categorisation, which helps people understand what it all means and why it was there in the first place.

There is no reason to remove FPUMode. You can just add "SveMode" to that list and make it (1 << 1) to make it explicit that this is bit pattern enum.


Repository:
  rL LLVM

https://reviews.llvm.org/D35118