r304493 - [AArch64] Add ARMv8.2-A FP16 vefctor intrinsics
Vedant Kumar via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 1 17:02:33 PDT 2017
Hi Abderrazek,
This commit results in test failures on our bots:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37166/ <http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37166/>
Could you take a look?
vedant
> On Jun 1, 2017, at 4:22 PM, Abderrazek Zaafrani via cfe-commits <cfe-commits at lists.llvm.org> wrote:
>
> Author: az
> Date: Thu Jun 1 18:22:29 2017
> New Revision: 304493
>
> URL: http://llvm.org/viewvc/llvm-project?rev=304493&view=rev
> Log:
> [AArch64] Add ARMv8.2-A FP16 vefctor intrinsics
>
> Added:
> cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
> Modified:
> cfe/trunk/include/clang/Basic/arm_neon.td
> cfe/trunk/lib/Basic/Targets.cpp
> cfe/trunk/lib/CodeGen/CGBuiltin.cpp
> cfe/trunk/lib/CodeGen/CodeGenModule.cpp
> cfe/trunk/lib/CodeGen/CodeGenTypeCache.h
> cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
> cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c
> cfe/trunk/utils/TableGen/NeonEmitter.cpp
>
> Modified: cfe/trunk/include/clang/Basic/arm_neon.td
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/include/clang/Basic/arm_neon.td (original)
> +++ cfe/trunk/include/clang/Basic/arm_neon.td Thu Jun 1 18:22:29 2017
> @@ -227,6 +227,7 @@ def OP_UNAVAILABLE : Operation {
> // u: unsigned integer (int/float args)
> // f: float (int args)
> // F: double (int args)
> +// H: half (int args)
> // d: default
> // g: default, ignore 'Q' size modifier.
> // j: default, force 'Q' size modifier.
> @@ -345,6 +346,7 @@ def OP_MLSLHi : Op<(call "vmlsl", $p0,
> (call "vget_high", $p2))>;
> def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>;
> def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>;
> +def OP_MULX_N : Op<(call "vmulx", $p0, (dup $p1))>;
> def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>;
> def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>;
> def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>;
> @@ -1661,3 +1663,186 @@ def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqr
> def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
> def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
> }
> +
> +// ARMv8.2-A FP16 intrinsics.
> +let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {
> +
> + // ARMv8.2-A FP16 one-operand vector intrinsics.
> +
> + // Comparison
> + def CMEQH : SInst<"vceqz", "ud", "hQh">;
> + def CMGEH : SInst<"vcgez", "ud", "hQh">;
> + def CMGTH : SInst<"vcgtz", "ud", "hQh">;
> + def CMLEH : SInst<"vclez", "ud", "hQh">;
> + def CMLTH : SInst<"vcltz", "ud", "hQh">;
> +
> + // Vector conversion
> + def VCVT_F16 : SInst<"vcvt_f16", "Hd", "sUsQsQUs">;
> + def VCVT_S16 : SInst<"vcvt_s16", "xd", "hQh">;
> + def VCVT_U16 : SInst<"vcvt_u16", "ud", "hQh">;
> + def VCVTA_S16 : SInst<"vcvta_s16", "xd", "hQh">;
> + def VCVTA_U16 : SInst<"vcvta_u16", "ud", "hQh">;
> + def VCVTM_S16 : SInst<"vcvtm_s16", "xd", "hQh">;
> + def VCVTM_U16 : SInst<"vcvtm_u16", "ud", "hQh">;
> + def VCVTN_S16 : SInst<"vcvtn_s16", "xd", "hQh">;
> + def VCVTN_U16 : SInst<"vcvtn_u16", "ud", "hQh">;
> + def VCVTP_S16 : SInst<"vcvtp_s16", "xd", "hQh">;
> + def VCVTP_U16 : SInst<"vcvtp_u16", "ud", "hQh">;
> +
> + // Vector rounding
> + def FRINTZH : SInst<"vrnd", "dd", "hQh">;
> + def FRINTNH : SInst<"vrndn", "dd", "hQh">;
> + def FRINTAH : SInst<"vrnda", "dd", "hQh">;
> + def FRINTPH : SInst<"vrndp", "dd", "hQh">;
> + def FRINTMH : SInst<"vrndm", "dd", "hQh">;
> + def FRINTXH : SInst<"vrndx", "dd", "hQh">;
> + def FRINTIH : SInst<"vrndi", "dd", "hQh">;
> +
> + // Misc.
> + def VABSH : SInst<"vabs", "dd", "hQh">;
> + def VNEGH : SOpInst<"vneg", "dd", "hQh", OP_NEG>;
> + def VRECPEH : SInst<"vrecpe", "dd", "hQh">;
> + def FRSQRTEH : SInst<"vrsqrte", "dd", "hQh">;
> + def FSQRTH : SInst<"vsqrt", "dd", "hQh">;
> +
> + // ARMv8.2-A FP16 two-operands vector intrinsics.
> +
> + // Misc.
> + def VADDH : SOpInst<"vadd", "ddd", "hQh", OP_ADD>;
> + def VABDH : SInst<"vabd", "ddd", "hQh">;
> + def VSUBH : SOpInst<"vsub", "ddd", "hQh", OP_SUB>;
> +
> + // Comparison
> + let InstName = "vacge" in {
> + def VCAGEH : SInst<"vcage", "udd", "hQh">;
> + def VCALEH : SInst<"vcale", "udd", "hQh">;
> + }
> + let InstName = "vacgt" in {
> + def VCAGTH : SInst<"vcagt", "udd", "hQh">;
> + def VCALTH : SInst<"vcalt", "udd", "hQh">;
> + }
> + def VCEQH : SOpInst<"vceq", "udd", "hQh", OP_EQ>;
> + def VCGEH : SOpInst<"vcge", "udd", "hQh", OP_GE>;
> + def VCGTH : SOpInst<"vcgt", "udd", "hQh", OP_GT>;
> + let InstName = "vcge" in
> + def VCLEH : SOpInst<"vcle", "udd", "hQh", OP_LE>;
> + let InstName = "vcgt" in
> + def VCLTH : SOpInst<"vclt", "udd", "hQh", OP_LT>;
> +
> + // Vector conversion
> + let isVCVT_N = 1 in {
> + def VCVT_N_F16 : SInst<"vcvt_n_f16", "Hdi", "sUsQsQUs">;
> + def VCVT_N_S16 : SInst<"vcvt_n_s16", "xdi", "hQh">;
> + def VCVT_N_U16 : SInst<"vcvt_n_u16", "udi", "hQh">;
> + }
> +
> + // Max/Min
> + def VMAXH : SInst<"vmax", "ddd", "hQh">;
> + def VMINH : SInst<"vmin", "ddd", "hQh">;
> + def FMAXNMH : SInst<"vmaxnm", "ddd", "hQh">;
> + def FMINNMH : SInst<"vminnm", "ddd", "hQh">;
> +
> + // Multiplication/Division
> + def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;
> + def MULXH : SInst<"vmulx", "ddd", "hQh">;
> + def FDIVH : IOpInst<"vdiv", "ddd", "hQh", OP_DIV>;
> +
> + // Pairwise addition
> + def VPADDH : SInst<"vpadd", "ddd", "hQh">;
> +
> + // Pairwise Max/Min
> + def VPMAXH : SInst<"vpmax", "ddd", "hQh">;
> + def VPMINH : SInst<"vpmin", "ddd", "hQh">;
> + // Pairwise MaxNum/MinNum
> + def FMAXNMPH : SInst<"vpmaxnm", "ddd", "hQh">;
> + def FMINNMPH : SInst<"vpminnm", "ddd", "hQh">;
> +
> + // Reciprocal/Sqrt
> + def VRECPSH : SInst<"vrecps", "ddd", "hQh">;
> + def VRSQRTSH : SInst<"vrsqrts", "ddd", "hQh">;
> +
> + // ARMv8.2-A FP16 three-operands vector intrinsics.
> +
> + // Vector fused multiply-add operations
> + def VFMAH : SInst<"vfma", "dddd", "hQh">;
> + def VFMSH : SOpInst<"vfms", "dddd", "hQh", OP_FMLS>;
> +
> + // ARMv8.2-A FP16 lane vector intrinsics.
> +
> + // FMA lane
> + def VFMA_LANEH : IInst<"vfma_lane", "dddgi", "hQh">;
> + def VFMA_LANEQH : IInst<"vfma_laneq", "dddji", "hQh">;
> +
> + // FMA lane with scalar argument
> + def FMLA_NH : SOpInst<"vfma_n", "ddds", "hQh", OP_FMLA_N>;
> + // Scalar floating point fused multiply-add (scalar, by element)
> + def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "sssdi", "Sh">;
> + def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "sssji", "Sh">;
> +
> + // FMS lane
> + def VFMS_LANEH : IOpInst<"vfms_lane", "dddgi", "hQh", OP_FMS_LN>;
> + def VFMS_LANEQH : IOpInst<"vfms_laneq", "dddji", "hQh", OP_FMS_LNQ>;
> + // FMS lane with scalar argument
> + def FMLS_NH : SOpInst<"vfms_n", "ddds", "hQh", OP_FMLS_N>;
> + // Scalar floating foint fused multiply-subtract (scalar, by element)
> + def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "sssdi", "Sh", OP_FMS_LN>;
> + def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "sssji", "Sh", OP_FMS_LNQ>;
> +
> + // Mul lane
> + def VMUL_LANEH : IOpInst<"vmul_lane", "ddgi", "hQh", OP_MUL_LN>;
> + def VMUL_LANEQH : IOpInst<"vmul_laneq", "ddji", "hQh", OP_MUL_LN>;
> + def VMUL_NH : IOpInst<"vmul_n", "dds", "hQh", OP_MUL_N>;
> + // Scalar floating point multiply (scalar, by element)
> + def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "ssdi", "Sh", OP_SCALAR_MUL_LN>;
> + def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "ssji", "Sh", OP_SCALAR_MUL_LN>;
> +
> + // Mulx lane
> + def VMULX_LANEH : IOpInst<"vmulx_lane", "ddgi", "hQh", OP_MULX_LN>;
> + def VMULX_LANEQH : IOpInst<"vmulx_laneq", "ddji", "hQh", OP_MULX_LN>;
> + def VMULX_NH : IOpInst<"vmulx_n", "dds", "hQh", OP_MULX_N>;
> + // TODO: Scalar floating point multiply extended (scalar, by element)
> + // Below ones are commented out because they need vmulx_f16(float16_t, float16_t)
> + // which will be implemented later with fp16 scalar intrinsic (arm_fp16.h)
> + //def SCALAR_FMULX_LANEH : IOpInst<"vmulx_lane", "ssdi", "Sh", OP_SCALAR_MUL_LN>;
> + //def SCALAR_FMULX_LANEQH : IOpInst<"vmulx_laneq", "ssji", "Sh", OP_SCALAR_MUL_LN>;
> +
> + // ARMv8.2-A FP16 reduction vector intrinsics.
> + def VMAXVH : SInst<"vmaxv", "sd", "hQh">;
> + def VMINVH : SInst<"vminv", "sd", "hQh">;
> + def FMAXNMVH : SInst<"vmaxnmv", "sd", "hQh">;
> + def FMINNMVH : SInst<"vminnmv", "sd", "hQh">;
> +
> + // Data processing intrinsics - section 5
> +
> + // Logical operations
> + let isHiddenLInst = 1 in
> + def VBSLH : SInst<"vbsl", "dudd", "hQh">;
> +
> + // Transposition operations
> + def VZIPH : WInst<"vzip", "2dd", "hQh">;
> + def VUZPH : WInst<"vuzp", "2dd", "hQh">;
> + def VTRNH : WInst<"vtrn", "2dd", "hQh">;
> +
> + // Set all lanes to same value.
> + /* Already implemented prior to ARMv8.2-A.
> + def VMOV_NH : WOpInst<"vmov_n", "ds", "hQh", OP_DUP>;
> + def VDUP_NH : WOpInst<"vdup_n", "ds", "hQh", OP_DUP>;
> + def VDUP_LANE1H : WOpInst<"vdup_lane", "dgi", "hQh", OP_DUP_LN>;*/
> +
> + // Vector Extract
> + def VEXTH : WInst<"vext", "dddi", "hQh">;
> +
> + // Reverse vector elements
> + def VREV64H : WOpInst<"vrev64", "dd", "hQh", OP_REV64>;
> +
> + // Permutation
> + def VTRN1H : SOpInst<"vtrn1", "ddd", "hQh", OP_TRN1>;
> + def VZIP1H : SOpInst<"vzip1", "ddd", "hQh", OP_ZIP1>;
> + def VUZP1H : SOpInst<"vuzp1", "ddd", "hQh", OP_UZP1>;
> + def VTRN2H : SOpInst<"vtrn2", "ddd", "hQh", OP_TRN2>;
> + def VZIP2H : SOpInst<"vzip2", "ddd", "hQh", OP_ZIP2>;
> + def VUZP2H : SOpInst<"vuzp2", "ddd", "hQh", OP_UZP2>;
> +
> + def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "sdi", "Sh">;
> + def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "sji", "Sh">;
> +}
>
> Modified: cfe/trunk/lib/Basic/Targets.cpp
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/lib/Basic/Targets.cpp (original)
> +++ cfe/trunk/lib/Basic/Targets.cpp Thu Jun 1 18:22:29 2017
> @@ -6151,6 +6151,8 @@ class AArch64TargetInfo : public TargetI
> unsigned Crypto;
> unsigned Unaligned;
> unsigned V8_1A;
> + unsigned V8_2A;
> + unsigned HasFP16;
>
> static const Builtin::Info BuiltinInfo[];
>
> @@ -6282,6 +6284,8 @@ public:
>
> if (V8_1A)
> Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
> + if (V8_2A && FPU == NeonMode && HasFP16)
> + Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");
>
> // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
> Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
> @@ -6309,6 +6313,8 @@ public:
> Crypto = 0;
> Unaligned = 1;
> V8_1A = 0;
> + V8_2A = 0;
> + HasFP16 = 0;
>
> for (const auto &Feature : Features) {
> if (Feature == "+neon")
> @@ -6321,6 +6327,10 @@ public:
> Unaligned = 0;
> if (Feature == "+v8.1a")
> V8_1A = 1;
> + if (Feature == "+v8.2a")
> + V8_2A = 1;
> + if (Feature == "+fp16")
> + HasFP16 = 1;
> }
>
> setDataLayout();
>
> Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
> +++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Jun 1 18:22:29 2017
> @@ -2955,8 +2955,9 @@ static llvm::VectorType *GetNeonType(Cod
> return llvm::VectorType::get(CGF->Int8Ty, V1Ty ? 1 : (8 << IsQuad));
> case NeonTypeFlags::Int16:
> case NeonTypeFlags::Poly16:
> - case NeonTypeFlags::Float16:
> return llvm::VectorType::get(CGF->Int16Ty, V1Ty ? 1 : (4 << IsQuad));
> + case NeonTypeFlags::Float16:
> + return llvm::VectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad));
> case NeonTypeFlags::Int32:
> return llvm::VectorType::get(CGF->Int32Ty, V1Ty ? 1 : (2 << IsQuad));
> case NeonTypeFlags::Int64:
> @@ -2979,6 +2980,8 @@ static llvm::VectorType *GetFloatNeonTyp
> NeonTypeFlags IntTypeFlags) {
> int IsQuad = IntTypeFlags.isQuad();
> switch (IntTypeFlags.getEltType()) {
> + case NeonTypeFlags::Int16:
> + return llvm::VectorType::get(CGF->HalfTy, (4 << IsQuad));
> case NeonTypeFlags::Int32:
> return llvm::VectorType::get(CGF->FloatTy, (2 << IsQuad));
> case NeonTypeFlags::Int64:
> @@ -3126,55 +3129,80 @@ static const NeonIntrinsicInfo ARMSIMDIn
> NEONMAP1(vcvt_f16_f32, arm_neon_vcvtfp2hf, 0),
> NEONMAP1(vcvt_f32_f16, arm_neon_vcvthf2fp, 0),
> NEONMAP0(vcvt_f32_v),
> + NEONMAP2(vcvt_n_f16_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvt_n_f32_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),
> + NEONMAP1(vcvt_n_s16_v, arm_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvt_n_s32_v, arm_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvt_n_s64_v, arm_neon_vcvtfp2fxs, 0),
> + NEONMAP1(vcvt_n_u16_v, arm_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvt_n_u32_v, arm_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvt_n_u64_v, arm_neon_vcvtfp2fxu, 0),
> + NEONMAP0(vcvt_s16_v),
> NEONMAP0(vcvt_s32_v),
> NEONMAP0(vcvt_s64_v),
> + NEONMAP0(vcvt_u16_v),
> NEONMAP0(vcvt_u32_v),
> NEONMAP0(vcvt_u64_v),
> + NEONMAP1(vcvta_s16_v, arm_neon_vcvtas, 0),
> NEONMAP1(vcvta_s32_v, arm_neon_vcvtas, 0),
> NEONMAP1(vcvta_s64_v, arm_neon_vcvtas, 0),
> NEONMAP1(vcvta_u32_v, arm_neon_vcvtau, 0),
> NEONMAP1(vcvta_u64_v, arm_neon_vcvtau, 0),
> + NEONMAP1(vcvtaq_s16_v, arm_neon_vcvtas, 0),
> NEONMAP1(vcvtaq_s32_v, arm_neon_vcvtas, 0),
> NEONMAP1(vcvtaq_s64_v, arm_neon_vcvtas, 0),
> + NEONMAP1(vcvtaq_u16_v, arm_neon_vcvtau, 0),
> NEONMAP1(vcvtaq_u32_v, arm_neon_vcvtau, 0),
> NEONMAP1(vcvtaq_u64_v, arm_neon_vcvtau, 0),
> + NEONMAP1(vcvtm_s16_v, arm_neon_vcvtms, 0),
> NEONMAP1(vcvtm_s32_v, arm_neon_vcvtms, 0),
> NEONMAP1(vcvtm_s64_v, arm_neon_vcvtms, 0),
> + NEONMAP1(vcvtm_u16_v, arm_neon_vcvtmu, 0),
> NEONMAP1(vcvtm_u32_v, arm_neon_vcvtmu, 0),
> NEONMAP1(vcvtm_u64_v, arm_neon_vcvtmu, 0),
> + NEONMAP1(vcvtmq_s16_v, arm_neon_vcvtms, 0),
> NEONMAP1(vcvtmq_s32_v, arm_neon_vcvtms, 0),
> NEONMAP1(vcvtmq_s64_v, arm_neon_vcvtms, 0),
> + NEONMAP1(vcvtmq_u16_v, arm_neon_vcvtmu, 0),
> NEONMAP1(vcvtmq_u32_v, arm_neon_vcvtmu, 0),
> NEONMAP1(vcvtmq_u64_v, arm_neon_vcvtmu, 0),
> + NEONMAP1(vcvtn_s16_v, arm_neon_vcvtns, 0),
> NEONMAP1(vcvtn_s32_v, arm_neon_vcvtns, 0),
> NEONMAP1(vcvtn_s64_v, arm_neon_vcvtns, 0),
> + NEONMAP1(vcvtn_u16_v, arm_neon_vcvtnu, 0),
> NEONMAP1(vcvtn_u32_v, arm_neon_vcvtnu, 0),
> NEONMAP1(vcvtn_u64_v, arm_neon_vcvtnu, 0),
> + NEONMAP1(vcvtnq_s16_v, arm_neon_vcvtns, 0),
> NEONMAP1(vcvtnq_s32_v, arm_neon_vcvtns, 0),
> NEONMAP1(vcvtnq_s64_v, arm_neon_vcvtns, 0),
> + NEONMAP1(vcvtnq_u16_v, arm_neon_vcvtnu, 0),
> NEONMAP1(vcvtnq_u32_v, arm_neon_vcvtnu, 0),
> NEONMAP1(vcvtnq_u64_v, arm_neon_vcvtnu, 0),
> + NEONMAP1(vcvtp_s16_v, arm_neon_vcvtps, 0),
> NEONMAP1(vcvtp_s32_v, arm_neon_vcvtps, 0),
> NEONMAP1(vcvtp_s64_v, arm_neon_vcvtps, 0),
> + NEONMAP1(vcvtp_u16_v, arm_neon_vcvtpu, 0),
> NEONMAP1(vcvtp_u32_v, arm_neon_vcvtpu, 0),
> NEONMAP1(vcvtp_u64_v, arm_neon_vcvtpu, 0),
> + NEONMAP1(vcvtpq_s16_v, arm_neon_vcvtps, 0),
> NEONMAP1(vcvtpq_s32_v, arm_neon_vcvtps, 0),
> NEONMAP1(vcvtpq_s64_v, arm_neon_vcvtps, 0),
> + NEONMAP1(vcvtpq_u16_v, arm_neon_vcvtpu, 0),
> NEONMAP1(vcvtpq_u32_v, arm_neon_vcvtpu, 0),
> NEONMAP1(vcvtpq_u64_v, arm_neon_vcvtpu, 0),
> NEONMAP0(vcvtq_f32_v),
> + NEONMAP2(vcvtq_n_f16_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvtq_n_f32_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),
> + NEONMAP1(vcvtq_n_s16_v, arm_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvtq_n_s32_v, arm_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvtq_n_s64_v, arm_neon_vcvtfp2fxs, 0),
> + NEONMAP1(vcvtq_n_u16_v, arm_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvtq_n_u32_v, arm_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvtq_n_u64_v, arm_neon_vcvtfp2fxu, 0),
> + NEONMAP0(vcvtq_s16_v),
> NEONMAP0(vcvtq_s32_v),
> NEONMAP0(vcvtq_s64_v),
> + NEONMAP0(vcvtq_u16_v),
> NEONMAP0(vcvtq_u32_v),
> NEONMAP0(vcvtq_u64_v),
> NEONMAP0(vext_v),
> @@ -3337,19 +3365,27 @@ static const NeonIntrinsicInfo AArch64SI
> NEONMAP1(vcnt_v, ctpop, Add1ArgType),
> NEONMAP1(vcntq_v, ctpop, Add1ArgType),
> NEONMAP1(vcvt_f16_f32, aarch64_neon_vcvtfp2hf, 0),
> + NEONMAP0(vcvt_f16_v),
> NEONMAP1(vcvt_f32_f16, aarch64_neon_vcvthf2fp, 0),
> NEONMAP0(vcvt_f32_v),
> + NEONMAP2(vcvt_n_f16_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvt_n_f32_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvt_n_f64_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> + NEONMAP1(vcvt_n_s16_v, aarch64_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvt_n_s32_v, aarch64_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvt_n_s64_v, aarch64_neon_vcvtfp2fxs, 0),
> + NEONMAP1(vcvt_n_u16_v, aarch64_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvt_n_u32_v, aarch64_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvt_n_u64_v, aarch64_neon_vcvtfp2fxu, 0),
> + NEONMAP0(vcvtq_f16_v),
> NEONMAP0(vcvtq_f32_v),
> + NEONMAP2(vcvtq_n_f16_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvtq_n_f32_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> NEONMAP2(vcvtq_n_f64_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),
> + NEONMAP1(vcvtq_n_s16_v, aarch64_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvtq_n_s32_v, aarch64_neon_vcvtfp2fxs, 0),
> NEONMAP1(vcvtq_n_s64_v, aarch64_neon_vcvtfp2fxs, 0),
> + NEONMAP1(vcvtq_n_u16_v, aarch64_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvtq_n_u32_v, aarch64_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvtq_n_u64_v, aarch64_neon_vcvtfp2fxu, 0),
> NEONMAP1(vcvtx_f32_v, aarch64_neon_fcvtxn, AddRetType | Add1ArgType),
> @@ -3817,9 +3853,20 @@ Value *CodeGenFunction::EmitCommonNeonBu
> case NEON::BI__builtin_neon_vcageq_v:
> case NEON::BI__builtin_neon_vcagt_v:
> case NEON::BI__builtin_neon_vcagtq_v: {
> - llvm::Type *VecFlt = llvm::VectorType::get(
> - VTy->getScalarSizeInBits() == 32 ? FloatTy : DoubleTy,
> - VTy->getNumElements());
> + llvm::Type *Ty;
> + switch (VTy->getScalarSizeInBits()) {
> + default: llvm_unreachable("unexpected type");
> + case 32:
> + Ty = FloatTy;
> + break;
> + case 64:
> + Ty = DoubleTy;
> + break;
> + case 16:
> + Ty = HalfTy;
> + break;
> + }
> + llvm::Type *VecFlt = llvm::VectorType::get(Ty, VTy->getNumElements());
> llvm::Type *Tys[] = { VTy, VecFlt };
> Function *F = CGM.getIntrinsic(LLVMIntrinsic, Tys);
> return EmitNeonCall(F, Ops, NameHint);
> @@ -3836,8 +3883,16 @@ Value *CodeGenFunction::EmitCommonNeonBu
> Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, Quad));
> return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")
> : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");
> + case NEON::BI__builtin_neon_vcvt_f16_v:
> + case NEON::BI__builtin_neon_vcvtq_f16_v:
> + Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
> + Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float16, false, Quad));
> + return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")
> + : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");
> + case NEON::BI__builtin_neon_vcvt_n_f16_v:
> case NEON::BI__builtin_neon_vcvt_n_f32_v:
> case NEON::BI__builtin_neon_vcvt_n_f64_v:
> + case NEON::BI__builtin_neon_vcvtq_n_f16_v:
> case NEON::BI__builtin_neon_vcvtq_n_f32_v:
> case NEON::BI__builtin_neon_vcvtq_n_f64_v: {
> llvm::Type *Tys[2] = { GetFloatNeonType(this, Type), Ty };
> @@ -3845,11 +3900,15 @@ Value *CodeGenFunction::EmitCommonNeonBu
> Function *F = CGM.getIntrinsic(Int, Tys);
> return EmitNeonCall(F, Ops, "vcvt_n");
> }
> + case NEON::BI__builtin_neon_vcvt_n_s16_v:
> case NEON::BI__builtin_neon_vcvt_n_s32_v:
> + case NEON::BI__builtin_neon_vcvt_n_u16_v:
> case NEON::BI__builtin_neon_vcvt_n_u32_v:
> case NEON::BI__builtin_neon_vcvt_n_s64_v:
> case NEON::BI__builtin_neon_vcvt_n_u64_v:
> + case NEON::BI__builtin_neon_vcvtq_n_s16_v:
> case NEON::BI__builtin_neon_vcvtq_n_s32_v:
> + case NEON::BI__builtin_neon_vcvtq_n_u16_v:
> case NEON::BI__builtin_neon_vcvtq_n_u32_v:
> case NEON::BI__builtin_neon_vcvtq_n_s64_v:
> case NEON::BI__builtin_neon_vcvtq_n_u64_v: {
> @@ -3861,44 +3920,63 @@ Value *CodeGenFunction::EmitCommonNeonBu
> case NEON::BI__builtin_neon_vcvt_u32_v:
> case NEON::BI__builtin_neon_vcvt_s64_v:
> case NEON::BI__builtin_neon_vcvt_u64_v:
> + case NEON::BI__builtin_neon_vcvt_s16_v:
> + case NEON::BI__builtin_neon_vcvt_u16_v:
> case NEON::BI__builtin_neon_vcvtq_s32_v:
> case NEON::BI__builtin_neon_vcvtq_u32_v:
> case NEON::BI__builtin_neon_vcvtq_s64_v:
> - case NEON::BI__builtin_neon_vcvtq_u64_v: {
> + case NEON::BI__builtin_neon_vcvtq_u64_v:
> + case NEON::BI__builtin_neon_vcvtq_s16_v:
> + case NEON::BI__builtin_neon_vcvtq_u16_v: {
> Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));
> return Usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt")
> : Builder.CreateFPToSI(Ops[0], Ty, "vcvt");
> }
> + case NEON::BI__builtin_neon_vcvta_s16_v:
> case NEON::BI__builtin_neon_vcvta_s32_v:
> case NEON::BI__builtin_neon_vcvta_s64_v:
> case NEON::BI__builtin_neon_vcvta_u32_v:
> case NEON::BI__builtin_neon_vcvta_u64_v:
> + case NEON::BI__builtin_neon_vcvtaq_s16_v:
> case NEON::BI__builtin_neon_vcvtaq_s32_v:
> case NEON::BI__builtin_neon_vcvtaq_s64_v:
> + case NEON::BI__builtin_neon_vcvtaq_u16_v:
> case NEON::BI__builtin_neon_vcvtaq_u32_v:
> case NEON::BI__builtin_neon_vcvtaq_u64_v:
> + case NEON::BI__builtin_neon_vcvtn_s16_v:
> case NEON::BI__builtin_neon_vcvtn_s32_v:
> case NEON::BI__builtin_neon_vcvtn_s64_v:
> + case NEON::BI__builtin_neon_vcvtn_u16_v:
> case NEON::BI__builtin_neon_vcvtn_u32_v:
> case NEON::BI__builtin_neon_vcvtn_u64_v:
> + case NEON::BI__builtin_neon_vcvtnq_s16_v:
> case NEON::BI__builtin_neon_vcvtnq_s32_v:
> case NEON::BI__builtin_neon_vcvtnq_s64_v:
> + case NEON::BI__builtin_neon_vcvtnq_u16_v:
> case NEON::BI__builtin_neon_vcvtnq_u32_v:
> case NEON::BI__builtin_neon_vcvtnq_u64_v:
> + case NEON::BI__builtin_neon_vcvtp_s16_v:
> case NEON::BI__builtin_neon_vcvtp_s32_v:
> case NEON::BI__builtin_neon_vcvtp_s64_v:
> + case NEON::BI__builtin_neon_vcvtp_u16_v:
> case NEON::BI__builtin_neon_vcvtp_u32_v:
> case NEON::BI__builtin_neon_vcvtp_u64_v:
> + case NEON::BI__builtin_neon_vcvtpq_s16_v:
> case NEON::BI__builtin_neon_vcvtpq_s32_v:
> case NEON::BI__builtin_neon_vcvtpq_s64_v:
> + case NEON::BI__builtin_neon_vcvtpq_u16_v:
> case NEON::BI__builtin_neon_vcvtpq_u32_v:
> case NEON::BI__builtin_neon_vcvtpq_u64_v:
> + case NEON::BI__builtin_neon_vcvtm_s16_v:
> case NEON::BI__builtin_neon_vcvtm_s32_v:
> case NEON::BI__builtin_neon_vcvtm_s64_v:
> + case NEON::BI__builtin_neon_vcvtm_u16_v:
> case NEON::BI__builtin_neon_vcvtm_u32_v:
> case NEON::BI__builtin_neon_vcvtm_u64_v:
> + case NEON::BI__builtin_neon_vcvtmq_s16_v:
> case NEON::BI__builtin_neon_vcvtmq_s32_v:
> case NEON::BI__builtin_neon_vcvtmq_s64_v:
> + case NEON::BI__builtin_neon_vcvtmq_u16_v:
> case NEON::BI__builtin_neon_vcvtmq_u32_v:
> case NEON::BI__builtin_neon_vcvtmq_u64_v: {
> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };
> @@ -6107,7 +6185,9 @@ Value *CodeGenFunction::EmitAArch64Built
> Ops[2] = EmitNeonSplat(Ops[2], cast<ConstantInt>(Ops[3]));
> return Builder.CreateCall(F, {Ops[2], Ops[1], Ops[0]});
> }
> + case NEON::BI__builtin_neon_vfmah_lane_f16:
> case NEON::BI__builtin_neon_vfmas_lane_f32:
> + case NEON::BI__builtin_neon_vfmah_laneq_f16:
> case NEON::BI__builtin_neon_vfmas_laneq_f32:
> case NEON::BI__builtin_neon_vfmad_lane_f64:
> case NEON::BI__builtin_neon_vfmad_laneq_f64: {
> @@ -6282,18 +6362,25 @@ Value *CodeGenFunction::EmitAArch64Built
> case NEON::BI__builtin_neon_vcvt_u32_v:
> case NEON::BI__builtin_neon_vcvt_s64_v:
> case NEON::BI__builtin_neon_vcvt_u64_v:
> + case NEON::BI__builtin_neon_vcvt_s16_v:
> + case NEON::BI__builtin_neon_vcvt_u16_v:
> case NEON::BI__builtin_neon_vcvtq_s32_v:
> case NEON::BI__builtin_neon_vcvtq_u32_v:
> case NEON::BI__builtin_neon_vcvtq_s64_v:
> - case NEON::BI__builtin_neon_vcvtq_u64_v: {
> + case NEON::BI__builtin_neon_vcvtq_u64_v:
> + case NEON::BI__builtin_neon_vcvtq_s16_v:
> + case NEON::BI__builtin_neon_vcvtq_u16_v: {
> Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));
> if (usgn)
> return Builder.CreateFPToUI(Ops[0], Ty);
> return Builder.CreateFPToSI(Ops[0], Ty);
> }
> + case NEON::BI__builtin_neon_vcvta_s16_v:
> case NEON::BI__builtin_neon_vcvta_s32_v:
> + case NEON::BI__builtin_neon_vcvtaq_s16_v:
> case NEON::BI__builtin_neon_vcvtaq_s32_v:
> case NEON::BI__builtin_neon_vcvta_u32_v:
> + case NEON::BI__builtin_neon_vcvtaq_u16_v:
> case NEON::BI__builtin_neon_vcvtaq_u32_v:
> case NEON::BI__builtin_neon_vcvta_s64_v:
> case NEON::BI__builtin_neon_vcvtaq_s64_v:
> @@ -6303,9 +6390,13 @@ Value *CodeGenFunction::EmitAArch64Built
> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };
> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvta");
> }
> + case NEON::BI__builtin_neon_vcvtm_s16_v:
> case NEON::BI__builtin_neon_vcvtm_s32_v:
> + case NEON::BI__builtin_neon_vcvtmq_s16_v:
> case NEON::BI__builtin_neon_vcvtmq_s32_v:
> + case NEON::BI__builtin_neon_vcvtm_u16_v:
> case NEON::BI__builtin_neon_vcvtm_u32_v:
> + case NEON::BI__builtin_neon_vcvtmq_u16_v:
> case NEON::BI__builtin_neon_vcvtmq_u32_v:
> case NEON::BI__builtin_neon_vcvtm_s64_v:
> case NEON::BI__builtin_neon_vcvtmq_s64_v:
> @@ -6315,9 +6406,13 @@ Value *CodeGenFunction::EmitAArch64Built
> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };
> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvtm");
> }
> + case NEON::BI__builtin_neon_vcvtn_s16_v:
> case NEON::BI__builtin_neon_vcvtn_s32_v:
> + case NEON::BI__builtin_neon_vcvtnq_s16_v:
> case NEON::BI__builtin_neon_vcvtnq_s32_v:
> + case NEON::BI__builtin_neon_vcvtn_u16_v:
> case NEON::BI__builtin_neon_vcvtn_u32_v:
> + case NEON::BI__builtin_neon_vcvtnq_u16_v:
> case NEON::BI__builtin_neon_vcvtnq_u32_v:
> case NEON::BI__builtin_neon_vcvtn_s64_v:
> case NEON::BI__builtin_neon_vcvtnq_s64_v:
> @@ -6327,9 +6422,13 @@ Value *CodeGenFunction::EmitAArch64Built
> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };
> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvtn");
> }
> + case NEON::BI__builtin_neon_vcvtp_s16_v:
> case NEON::BI__builtin_neon_vcvtp_s32_v:
> + case NEON::BI__builtin_neon_vcvtpq_s16_v:
> case NEON::BI__builtin_neon_vcvtpq_s32_v:
> + case NEON::BI__builtin_neon_vcvtp_u16_v:
> case NEON::BI__builtin_neon_vcvtp_u32_v:
> + case NEON::BI__builtin_neon_vcvtpq_u16_v:
> case NEON::BI__builtin_neon_vcvtpq_u32_v:
> case NEON::BI__builtin_neon_vcvtp_s64_v:
> case NEON::BI__builtin_neon_vcvtpq_s64_v:
> @@ -6502,6 +6601,24 @@ Value *CodeGenFunction::EmitAArch64Built
> Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");
> return Builder.CreateTrunc(Ops[0], Int16Ty);
> }
> + case NEON::BI__builtin_neon_vmaxv_f16: {
> + Int = Intrinsic::aarch64_neon_fmaxv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 4);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vmaxvq_f16: {
> + Int = Intrinsic::aarch64_neon_fmaxv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 8);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> case NEON::BI__builtin_neon_vminv_u8: {
> Int = Intrinsic::aarch64_neon_uminv;
> Ty = Int32Ty;
> @@ -6574,6 +6691,60 @@ Value *CodeGenFunction::EmitAArch64Built
> Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");
> return Builder.CreateTrunc(Ops[0], Int16Ty);
> }
> + case NEON::BI__builtin_neon_vminv_f16: {
> + Int = Intrinsic::aarch64_neon_fminv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 4);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vminvq_f16: {
> + Int = Intrinsic::aarch64_neon_fminv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 8);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vmaxnmv_f16: {
> + Int = Intrinsic::aarch64_neon_fmaxnmv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 4);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxnmv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vmaxnmvq_f16: {
> + Int = Intrinsic::aarch64_neon_fmaxnmv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 8);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxnmv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vminnmv_f16: {
> + Int = Intrinsic::aarch64_neon_fminnmv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 4);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminnmv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> + case NEON::BI__builtin_neon_vminnmvq_f16: {
> + Int = Intrinsic::aarch64_neon_fminnmv;
> + Ty = HalfTy;
> + VTy = llvm::VectorType::get(HalfTy, 8);
> + llvm::Type *Tys[2] = { Ty, VTy };
> + Ops.push_back(EmitScalarExpr(E->getArg(0)));
> + Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminnmv");
> + return Builder.CreateTrunc(Ops[0], HalfTy);
> + }
> case NEON::BI__builtin_neon_vmul_n_f64: {
> Ops[0] = Builder.CreateBitCast(Ops[0], DoubleTy);
> Value *RHS = Builder.CreateBitCast(EmitScalarExpr(E->getArg(1)), DoubleTy);
>
> Modified: cfe/trunk/lib/CodeGen/CodeGenModule.cpp
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/lib/CodeGen/CodeGenModule.cpp (original)
> +++ cfe/trunk/lib/CodeGen/CodeGenModule.cpp Thu Jun 1 18:22:29 2017
> @@ -98,6 +98,7 @@ CodeGenModule::CodeGenModule(ASTContext
> Int16Ty = llvm::Type::getInt16Ty(LLVMContext);
> Int32Ty = llvm::Type::getInt32Ty(LLVMContext);
> Int64Ty = llvm::Type::getInt64Ty(LLVMContext);
> + HalfTy = llvm::Type::getHalfTy(LLVMContext);
> FloatTy = llvm::Type::getFloatTy(LLVMContext);
> DoubleTy = llvm::Type::getDoubleTy(LLVMContext);
> PointerWidthInBits = C.getTargetInfo().getPointerWidth(0);
>
> Modified: cfe/trunk/lib/CodeGen/CodeGenTypeCache.h
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenTypeCache.h?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/lib/CodeGen/CodeGenTypeCache.h (original)
> +++ cfe/trunk/lib/CodeGen/CodeGenTypeCache.h Thu Jun 1 18:22:29 2017
> @@ -36,7 +36,7 @@ struct CodeGenTypeCache {
> /// i8, i16, i32, and i64
> llvm::IntegerType *Int8Ty, *Int16Ty, *Int32Ty, *Int64Ty;
> /// float, double
> - llvm::Type *FloatTy, *DoubleTy;
> + llvm::Type *HalfTy, *FloatTy, *DoubleTy;
>
> /// int
> llvm::IntegerType *IntTy;
>
> Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
> +++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Thu Jun 1 18:22:29 2017
> @@ -9037,10 +9037,9 @@ int64x2_t test_vld1q_s64(int64_t const *
>
> // CHECK-LABEL: @test_vld1q_f16(
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
> -// CHECK: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
> -// CHECK: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>
> -// CHECK: ret <8 x half> [[TMP3]]
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
> +// CHECK: [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]
> +// CHECK: ret <8 x half> [[TMP2]]
> float16x8_t test_vld1q_f16(float16_t const *a) {
> return vld1q_f16(a);
> }
> @@ -9152,10 +9151,9 @@ int64x1_t test_vld1_s64(int64_t const *a
>
> // CHECK-LABEL: @test_vld1_f16(
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i16>*
> -// CHECK: [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]]
> -// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
> -// CHECK: ret <4 x half> [[TMP3]]
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*
> +// CHECK: [[TMP2:%.*]] = load <4 x half>, <4 x half>* [[TMP1]]
> +// CHECK: ret <4 x half> [[TMP2]]
> float16x4_t test_vld1_f16(float16_t const *a) {
> return vld1_f16(a);
> }
> @@ -9342,10 +9340,10 @@ int64x2x2_t test_vld2q_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*
> -// CHECK: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0v8i16(<8 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], { <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*
> +// CHECK: [[VLD2:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half> } [[VLD2]], { <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)
> @@ -9573,10 +9571,10 @@ int64x1x2_t test_vld2_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*
> -// CHECK: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0v4i16(<4 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], { <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*
> +// CHECK: [[VLD2:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half> } [[VLD2]], { <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)
> @@ -9804,10 +9802,10 @@ int64x2x3_t test_vld3q_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*
> -// CHECK: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0v8i16(<8 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*
> +// CHECK: [[VLD3:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)
> @@ -10035,10 +10033,10 @@ int64x1x3_t test_vld3_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*
> -// CHECK: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0v4i16(<4 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*
> +// CHECK: [[VLD3:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)
> @@ -10266,10 +10264,10 @@ int64x2x4_t test_vld4q_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*
> -// CHECK: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0v8i16(<8 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*
> +// CHECK: [[VLD4:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)
> @@ -10497,10 +10495,10 @@ int64x1x4_t test_vld4_s64(int64_t const
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*
> -// CHECK: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*
> +// CHECK: [[VLD4:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 x half>* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)
> @@ -10666,9 +10664,9 @@ void test_vst1q_s64(int64_t *a, int64x2_
> // CHECK-LABEL: @test_vst1q_f16(
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
> -// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
> -// CHECK: store <8 x i16> [[TMP3]], <8 x i16>* [[TMP2]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: store <8 x half> [[TMP3]], <8 x half>* [[TMP2]]
> // CHECK: ret void
> void test_vst1q_f16(float16_t *a, float16x8_t b) {
> vst1q_f16(a, b);
> @@ -10800,9 +10798,9 @@ void test_vst1_s64(int64_t *a, int64x1_t
> // CHECK-LABEL: @test_vst1_f16(
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <4 x i16>*
> -// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> -// CHECK: store <4 x i16> [[TMP3]], <4 x i16>* [[TMP2]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: store <4 x half> [[TMP3]], <4 x half>* [[TMP2]]
> // CHECK: ret void
> void test_vst1_f16(float16_t *a, float16x4_t b) {
> vst1_f16(a, b);
> @@ -11056,9 +11054,9 @@ void test_vst2q_s64(int64_t *a, int64x2x
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16
> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st2.v8i16.p0i8(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i8* [[TMP2]])
> +// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st2.v8f16.p0i8(<8 x half> [[TMP7]], <8 x half> [[TMP8]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst2q_f16(float16_t *a, float16x8x2_t b) {
> vst2q_f16(a, b);
> @@ -11366,9 +11364,9 @@ void test_vst2_s64(int64_t *a, int64x1x2
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8
> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st2.v4i16.p0i8(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i8* [[TMP2]])
> +// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st2.v4f16.p0i8(<4 x half> [[TMP7]], <4 x half> [[TMP8]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst2_f16(float16_t *a, float16x4x2_t b) {
> vst2_f16(a, b);
> @@ -11716,10 +11714,10 @@ void test_vst3q_s64(int64_t *a, int64x2x
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16
> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st3.v8i16.p0i8(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i8* [[TMP2]])
> +// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st3.v8f16.p0i8(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst3q_f16(float16_t *a, float16x8x3_t b) {
> vst3q_f16(a, b);
> @@ -12085,10 +12083,10 @@ void test_vst3_s64(int64_t *a, int64x1x3
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8
> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st3.v4i16.p0i8(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i8* [[TMP2]])
> +// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st3.v4f16.p0i8(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst3_f16(float16_t *a, float16x4x3_t b) {
> vst3_f16(a, b);
> @@ -12494,11 +12492,11 @@ void test_vst4q_s64(int64_t *a, int64x2x
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16
> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st4.v8i16.p0i8(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i8* [[TMP2]])
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st4.v8f16.p0i8(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst4q_f16(float16_t *a, float16x8x4_t b) {
> vst4q_f16(a, b);
> @@ -12922,11 +12920,11 @@ void test_vst4_s64(int64_t *a, int64x1x4
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8
> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st4.v4i16.p0i8(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i8* [[TMP2]])
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st4.v4f16.p0i8(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], i8* [[TMP2]])
> // CHECK: ret void
> void test_vst4_f16(float16_t *a, float16x4x4_t b) {
> vst4_f16(a, b);
> @@ -13208,10 +13206,10 @@ int64x2x2_t test_vld1q_s64_x2(int64_t co
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)
> @@ -13454,10 +13452,10 @@ int64x1x2_t test_vld1_s64_x2(int64_t con
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)
> @@ -13700,10 +13698,10 @@ int64x2x3_t test_vld1q_s64_x3(int64_t co
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)
> @@ -13946,10 +13944,10 @@ int64x1x3_t test_vld1_s64_x3(int64_t con
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)
> @@ -14192,10 +14190,10 @@ int64x2x4_t test_vld1q_s64_x4(int64_t co
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)
> @@ -14438,10 +14436,10 @@ int64x1x4_t test_vld1_s64_x4(int64_t con
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)
> @@ -14752,10 +14750,10 @@ void test_vst1q_s64_x2(int64_t *a, int64
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16
> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i16* [[TMP9]])
> +// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x2.v8f16.p0f16(<8 x half> [[TMP7]], <8 x half> [[TMP8]], half* [[TMP9]])
> // CHECK: ret void
> void test_vst1q_f16_x2(float16_t *a, float16x8x2_t b) {
> vst1q_f16_x2(a, b);
> @@ -15098,10 +15096,10 @@ void test_vst1_s64_x2(int64_t *a, int64x
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8
> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i16* [[TMP9]])
> +// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x2.v4f16.p0f16(<4 x half> [[TMP7]], <4 x half> [[TMP8]], half* [[TMP9]])
> // CHECK: ret void
> void test_vst1_f16_x2(float16_t *a, float16x4x2_t b) {
> vst1_f16_x2(a, b);
> @@ -15484,11 +15482,11 @@ void test_vst1q_s64_x3(int64_t *a, int64
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16
> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i16* [[TMP12]])
> +// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x3.v8f16.p0f16(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], half* [[TMP12]])
> // CHECK: ret void
> void test_vst1q_f16_x3(float16_t *a, float16x8x3_t b) {
> vst1q_f16_x3(a, b);
> @@ -15894,11 +15892,11 @@ void test_vst1_s64_x3(int64_t *a, int64x
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8
> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i16* [[TMP12]])
> +// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x3.v4f16.p0f16(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], half* [[TMP12]])
> // CHECK: ret void
> void test_vst1_f16_x3(float16_t *a, float16x4x3_t b) {
> vst1_f16_x3(a, b);
> @@ -16344,12 +16342,12 @@ void test_vst1q_s64_x4(int64_t *a, int64
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16
> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16>
> -// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i16* [[TMP15]])
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half>
> +// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x4.v8f16.p0f16(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], half* [[TMP15]])
> // CHECK: ret void
> void test_vst1q_f16_x4(float16_t *a, float16x8x4_t b) {
> vst1q_f16_x4(a, b);
> @@ -16818,12 +16816,12 @@ void test_vst1_s64_x4(int64_t *a, int64x
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8
> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16>
> -// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to i16*
> -// CHECK: call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i16* [[TMP15]])
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half>
> +// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to half*
> +// CHECK: call void @llvm.aarch64.neon.st1x4.v4f16.p0f16(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], half* [[TMP15]])
> // CHECK: ret void
> void test_vst1_f16_x4(float16_t *a, float16x4x4_t b) {
> vst1_f16_x4(a, b);
>
> Modified: cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c (original)
> +++ cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c Thu Jun 1 18:22:29 2017
> @@ -90,12 +90,11 @@ int64x2_t test_vld1q_dup_s64(int64_t *a
>
> // CHECK-LABEL: define <8 x half> @test_vld1q_dup_f16(half* %a) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]]
> -// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0
> -// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer
> -// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half>
> -// CHECK: ret <8 x half> [[TMP4]]
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]]
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0
> +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer
> +// CHECK: ret <8 x half> [[LANE]]
> float16x8_t test_vld1q_dup_f16(float16_t *a) {
> return vld1q_dup_f16(a);
> }
> @@ -239,12 +238,11 @@ int64x1_t test_vld1_dup_s64(int64_t *a)
>
> // CHECK-LABEL: define <4 x half> @test_vld1_dup_f16(half* %a) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]]
> -// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0
> -// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer
> -// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half>
> -// CHECK: ret <4 x half> [[TMP4]]
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]]
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer
> +// CHECK: ret <4 x half> [[LANE]]
> float16x4_t test_vld1_dup_f16(float16_t *a) {
> return vld1_dup_f16(a);
> }
> @@ -447,10 +445,10 @@ int64x2x2_t test_vld2q_dup_s64(int64_t
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], { <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD2:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half> } [[VLD2]], { <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)
> @@ -693,10 +691,10 @@ int64x1x2_t test_vld2_dup_s64(int64_t *
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], { <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD2:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half> } [[VLD2]], { <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)
> @@ -947,10 +945,10 @@ int64x2x3_t test_vld3q_dup_s64(int64_t
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD3:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)
> @@ -1207,10 +1205,10 @@ int64x1x3_t test_vld3_dup_s64(int64_t *
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD3:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)
> @@ -1459,10 +1457,10 @@ int64x2x4_t test_vld4q_dup_s64(int64_t
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD4:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)
> @@ -1705,10 +1703,10 @@ int64x1x4_t test_vld4_dup_s64(int64_t *
> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8
> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*
> -// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*
> -// CHECK: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* [[TMP2]])
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]
> +// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*
> +// CHECK: [[VLD4:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half* [[TMP2]])
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]
> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)
> @@ -1897,12 +1895,11 @@ int64x2_t test_vld1q_lane_s64(int64_t *
> // CHECK-LABEL: define <8 x half> @test_vld1q_lane_f16(half* %a, <8 x half> %b) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]]
> -// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP4]], i32 7
> -// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[VLD1_LANE]] to <8 x half>
> -// CHECK: ret <8 x half> [[TMP5]]
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]]
> +// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP4]], i32 7
> +// CHECK: ret <8 x half> [[VLD1_LANE]]
> float16x8_t test_vld1q_lane_f16(float16_t *a, float16x8_t b) {
> return vld1q_lane_f16(a, b, 7);
> }
> @@ -2054,12 +2051,11 @@ int64x1_t test_vld1_lane_s64(int64_t *a
> // CHECK-LABEL: define <4 x half> @test_vld1_lane_f16(half* %a, <4 x half> %b) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> -// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]]
> -// CHECK: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[TMP4]], i32 3
> -// CHECK: [[TMP5:%.*]] = bitcast <4 x i16> [[VLD1_LANE]] to <4 x half>
> -// CHECK: ret <4 x half> [[TMP5]]
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]]
> +// CHECK: [[VLD1_LANE:%.*]] = insertelement <4 x half> [[TMP2]], half [[TMP4]], i32 3
> +// CHECK: ret <4 x half> [[VLD1_LANE]]
> float16x4_t test_vld1_lane_f16(float16_t *a, float16x4_t b) {
> return vld1_lane_f16(a, b, 3);
> }
> @@ -2495,11 +2491,11 @@ int64x2x2_t test_vld2q_lane_s64(int64_t
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP6:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16
> // CHECK: [[TMP7:%.*]] = bitcast <8 x half> [[TMP6]] to <16 x i8>
> -// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16>
> -// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16>
> -// CHECK: [[VLD2_LANE:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i8(<8 x i16> [[TMP8]], <8 x i16> [[TMP9]], i64 7, i8* [[TMP3]])
> -// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2_LANE]], { <8 x i16>, <8 x i16> }* [[TMP10]]
> +// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
> +// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half>
> +// CHECK: [[VLD2_LANE:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0i8(<8 x half> [[TMP8]], <8 x half> [[TMP9]], i64 7, i8* [[TMP3]])
> +// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half> } [[VLD2_LANE]], { <8 x half>, <8 x half> }* [[TMP10]]
> // CHECK: [[TMP11:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP12:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP11]], i8* [[TMP12]], i64 32, i32 16, i1 false)
> @@ -2927,11 +2923,11 @@ int64x1x2_t test_vld2_lane_s64(int64_t
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP6:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8
> // CHECK: [[TMP7:%.*]] = bitcast <4 x half> [[TMP6]] to <8 x i8>
> -// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>
> -// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>
> -// CHECK: [[VLD2_LANE:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i8(<4 x i16> [[TMP8]], <4 x i16> [[TMP9]], i64 3, i8* [[TMP3]])
> -// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2_LANE]], { <4 x i16>, <4 x i16> }* [[TMP10]]
> +// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
> +// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>
> +// CHECK: [[VLD2_LANE:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0i8(<4 x half> [[TMP8]], <4 x half> [[TMP9]], i64 3, i8* [[TMP3]])
> +// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half> } [[VLD2_LANE]], { <4 x half>, <4 x half> }* [[TMP10]]
> // CHECK: [[TMP11:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> // CHECK: [[TMP12:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP11]], i8* [[TMP12]], i64 16, i32 8, i1 false)
> @@ -3364,12 +3360,12 @@ int64x2x3_t test_vld3q_lane_s64(int64_t
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP8:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16
> // CHECK: [[TMP9:%.*]] = bitcast <8 x half> [[TMP8]] to <16 x i8>
> -// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x i16>
> -// CHECK: [[VLD3_LANE:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i8(<8 x i16> [[TMP10]], <8 x i16> [[TMP11]], <8 x i16> [[TMP12]], i64 7, i8* [[TMP3]])
> -// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3_LANE]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP13]]
> +// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x half>
> +// CHECK: [[VLD3_LANE:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0i8(<8 x half> [[TMP10]], <8 x half> [[TMP11]], <8 x half> [[TMP12]], i64 7, i8* [[TMP3]])
> +// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3_LANE]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP13]]
> // CHECK: [[TMP14:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP15:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP14]], i8* [[TMP15]], i64 48, i32 16, i1 false)
> @@ -3889,12 +3885,12 @@ int64x1x3_t test_vld3_lane_s64(int64_t
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP8:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8
> // CHECK: [[TMP9:%.*]] = bitcast <4 x half> [[TMP8]] to <8 x i8>
> -// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x i16>
> -// CHECK: [[VLD3_LANE:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i8(<4 x i16> [[TMP10]], <4 x i16> [[TMP11]], <4 x i16> [[TMP12]], i64 3, i8* [[TMP3]])
> -// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP13]]
> +// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x half>
> +// CHECK: [[VLD3_LANE:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0i8(<4 x half> [[TMP10]], <4 x half> [[TMP11]], <4 x half> [[TMP12]], i64 3, i8* [[TMP3]])
> +// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3_LANE]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP13]]
> // CHECK: [[TMP14:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*
> // CHECK: [[TMP15:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP14]], i8* [[TMP15]], i64 24, i32 8, i1 false)
> @@ -4454,13 +4450,13 @@ int64x2x4_t test_vld4q_lane_s64(int64_t
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP10:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16
> // CHECK: [[TMP11:%.*]] = bitcast <8 x half> [[TMP10]] to <16 x i8>
> -// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x i16>
> -// CHECK: [[TMP15:%.*]] = bitcast <16 x i8> [[TMP11]] to <8 x i16>
> -// CHECK: [[VLD4_LANE:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i8(<8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], <8 x i16> [[TMP15]], i64 7, i8* [[TMP3]])
> -// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*
> -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4_LANE]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP16]]
> +// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x half>
> +// CHECK: [[TMP15:%.*]] = bitcast <16 x i8> [[TMP11]] to <8 x half>
> +// CHECK: [[VLD4_LANE:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0i8(<8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], <8 x half> [[TMP15]], i64 7, i8* [[TMP3]])
> +// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*
> +// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4_LANE]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP16]]
> // CHECK: [[TMP17:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP18:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP17]], i8* [[TMP18]], i64 64, i32 16, i1 false)
> @@ -5043,13 +5039,13 @@ int64x1x4_t test_vld4_lane_s64(int64_t
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP10:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8
> // CHECK: [[TMP11:%.*]] = bitcast <4 x half> [[TMP10]] to <8 x i8>
> -// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x i16>
> -// CHECK: [[TMP15:%.*]] = bitcast <8 x i8> [[TMP11]] to <4 x i16>
> -// CHECK: [[VLD4_LANE:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i8(<4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], <4 x i16> [[TMP15]], i64 3, i8* [[TMP3]])
> -// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*
> -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP16]]
> +// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x half>
> +// CHECK: [[TMP15:%.*]] = bitcast <8 x i8> [[TMP11]] to <4 x half>
> +// CHECK: [[VLD4_LANE:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0i8(<4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], <4 x half> [[TMP15]], i64 3, i8* [[TMP3]])
> +// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*
> +// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP16]]
> // CHECK: [[TMP17:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*
> // CHECK: [[TMP18:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*
> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP17]], i8* [[TMP18]], i64 32, i32 8, i1 false)
> @@ -5361,10 +5357,10 @@ void test_vst1q_lane_s64(int64_t *a, in
> // CHECK-LABEL: define void @test_vst1q_lane_f16(half* %a, <8 x half> %b) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
> -// CHECK: [[TMP3:%.*]] = extractelement <8 x i16> [[TMP2]], i32 7
> -// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: store i16 [[TMP3]], i16* [[TMP4]]
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP3:%.*]] = extractelement <8 x half> [[TMP2]], i32 7
> +// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: store half [[TMP3]], half* [[TMP4]]
> // CHECK: ret void
> void test_vst1q_lane_f16(float16_t *a, float16x8_t b) {
> vst1q_lane_f16(a, b, 7);
> @@ -5517,10 +5513,10 @@ void test_vst1_lane_s64(int64_t *a, int
> // CHECK-LABEL: define void @test_vst1_lane_f16(half* %a, <4 x half> %b) #0 {
> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*
> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> -// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> -// CHECK: [[TMP3:%.*]] = extractelement <4 x i16> [[TMP2]], i32 3
> -// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to i16*
> -// CHECK: store i16 [[TMP3]], i16* [[TMP4]]
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP3:%.*]] = extractelement <4 x half> [[TMP2]], i32 3
> +// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to half*
> +// CHECK: store half [[TMP3]], half* [[TMP4]]
> // CHECK: ret void
> void test_vst1_lane_f16(float16_t *a, float16x4_t b) {
> vst1_lane_f16(a, b, 3);
> @@ -5789,9 +5785,9 @@ void test_vst2q_lane_s64(int64_t *a, in
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16
> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st2lane.v8i16.p0i8(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i64 7, i8* [[TMP2]])
> +// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st2lane.v8f16.p0i8(<8 x half> [[TMP7]], <8 x half> [[TMP8]], i64 7, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst2q_lane_f16(float16_t *a, float16x8x2_t b) {
> vst2q_lane_f16(a, b, 7);
> @@ -6124,9 +6120,9 @@ void test_vst2_lane_s64(int64_t *a, int
> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1
> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8
> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8>
> -// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st2lane.v4i16.p0i8(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i64 3, i8* [[TMP2]])
> +// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st2lane.v4f16.p0i8(<4 x half> [[TMP7]], <4 x half> [[TMP8]], i64 3, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst2_lane_f16(float16_t *a, float16x4x2_t b) {
> vst2_lane_f16(a, b, 3);
> @@ -6499,10 +6495,10 @@ void test_vst3q_lane_s64(int64_t *a, in
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16
> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st3lane.v8i16.p0i8(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i64 7, i8* [[TMP2]])
> +// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st3lane.v8f16.p0i8(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], i64 7, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst3q_lane_f16(float16_t *a, float16x8x3_t b) {
> vst3q_lane_f16(a, b, 7);
> @@ -6898,10 +6894,10 @@ void test_vst3_lane_s64(int64_t *a, int
> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2
> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8
> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8>
> -// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st3lane.v4i16.p0i8(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i64 3, i8* [[TMP2]])
> +// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st3lane.v4f16.p0i8(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i64 3, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst3_lane_f16(float16_t *a, float16x4x3_t b) {
> vst3_lane_f16(a, b, 3);
> @@ -7337,11 +7333,11 @@ void test_vst4q_lane_s64(int64_t *a, in
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16
> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st4lane.v8i16.p0i8(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i64 7, i8* [[TMP2]])
> +// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half>
> +// CHECK: call void @llvm.aarch64.neon.st4lane.v8f16.p0i8(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], i64 7, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst4q_lane_f16(float16_t *a, float16x8x4_t b) {
> vst4q_lane_f16(a, b, 7);
> @@ -7800,11 +7796,11 @@ void test_vst4_lane_s64(int64_t *a, int
> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3
> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8
> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8>
> -// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16>
> -// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16>
> -// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16>
> -// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16>
> -// CHECK: call void @llvm.aarch64.neon.st4lane.v4i16.p0i8(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i64 3, i8* [[TMP2]])
> +// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half>
> +// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half>
> +// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half>
> +// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half>
> +// CHECK: call void @llvm.aarch64.neon.st4lane.v4f16.p0i8(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], i64 3, i8* [[TMP2]])
> // CHECK: ret void
> void test_vst4_lane_f16(float16_t *a, float16x4x4_t b) {
> vst4_lane_f16(a, b, 3);
>
> Added: cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c?rev=304493&view=auto
> ==============================================================================
> --- cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c (added)
> +++ cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c Thu Jun 1 18:22:29 2017
> @@ -0,0 +1,1633 @@
> +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fp16 -target-feature +v8.2a \
> +// RUN: -fallow-half-arguments-and-returns -S -emit-llvm -o - %s \
> +// RUN: | opt -S -mem2reg \
> +// RUN: | FileCheck %s
> +
> +// REQUIRES: aarch64-registered-target
> +
> +#include <arm_neon.h>
> +
> +// CHECK-LABEL: test_vabs_f16
> +// CHECK: [[ABS:%.*]] = call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[ABS]]
> +float16x4_t test_vabs_f16(float16x4_t a) {
> + return vabs_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vabsq_f16
> +// CHECK: [[ABS:%.*]] = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[ABS]]
> +float16x8_t test_vabsq_f16(float16x8_t a) {
> + return vabsq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vceqz_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oeq <4 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vceqz_f16(float16x4_t a) {
> + return vceqz_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vceqzq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oeq <8 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vceqzq_f16(float16x8_t a) {
> + return vceqzq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcgez_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oge <4 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcgez_f16(float16x4_t a) {
> + return vcgez_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcgezq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oge <8 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcgezq_f16(float16x8_t a) {
> + return vcgezq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcgtz_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ogt <4 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcgtz_f16(float16x4_t a) {
> + return vcgtz_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcgtzq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ogt <8 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcgtzq_f16(float16x8_t a) {
> + return vcgtzq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vclez_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ole <4 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vclez_f16(float16x4_t a) {
> + return vclez_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vclezq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ole <8 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vclezq_f16(float16x8_t a) {
> + return vclezq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcltz_f16
> +// CHECK: [[TMP1:%.*]] = fcmp olt <4 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcltz_f16(float16x4_t a) {
> + return vcltz_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcltzq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp olt <8 x half> %a, zeroinitializer
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcltzq_f16(float16x8_t a) {
> + return vcltzq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvt_f16_s16
> +// CHECK: [[VCVT:%.*]] = sitofp <4 x i16> %a to <4 x half>
> +// CHECK: ret <4 x half> [[VCVT]]
> +float16x4_t test_vcvt_f16_s16 (int16x4_t a) {
> + return vcvt_f16_s16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_f16_s16
> +// CHECK: [[VCVT:%.*]] = sitofp <8 x i16> %a to <8 x half>
> +// CHECK: ret <8 x half> [[VCVT]]
> +float16x8_t test_vcvtq_f16_s16 (int16x8_t a) {
> + return vcvtq_f16_s16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvt_f16_u16
> +// CHECK: [[VCVT:%.*]] = uitofp <4 x i16> %a to <4 x half>
> +// CHECK: ret <4 x half> [[VCVT]]
> +float16x4_t test_vcvt_f16_u16 (uint16x4_t a) {
> + return vcvt_f16_u16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_f16_u16
> +// CHECK: [[VCVT:%.*]] = uitofp <8 x i16> %a to <8 x half>
> +// CHECK: ret <8 x half> [[VCVT]]
> +float16x8_t test_vcvtq_f16_u16 (uint16x8_t a) {
> + return vcvtq_f16_u16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvt_s16_f16
> +// CHECK: [[VCVT:%.*]] = fptosi <4 x half> %a to <4 x i16>
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvt_s16_f16 (float16x4_t a) {
> + return vcvt_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_s16_f16
> +// CHECK: [[VCVT:%.*]] = fptosi <8 x half> %a to <8 x i16>
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtq_s16_f16 (float16x8_t a) {
> + return vcvtq_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvt_u16_f16
> +// CHECK: [[VCVT:%.*]] = fptoui <4 x half> %a to <4 x i16>
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvt_u16_f16 (float16x4_t a) {
> + return vcvt_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_u16_f16
> +// CHECK: [[VCVT:%.*]] = fptoui <8 x half> %a to <8 x i16>
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtq_u16_f16 (float16x8_t a) {
> + return vcvtq_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvta_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvta_s16_f16 (float16x4_t a) {
> + return vcvta_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtaq_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtas.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtaq_s16_f16 (float16x8_t a) {
> + return vcvtaq_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtm_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvtm_s16_f16 (float16x4_t a) {
> + return vcvtm_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtmq_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtms.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtmq_s16_f16 (float16x8_t a) {
> + return vcvtmq_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtm_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +uint16x4_t test_vcvtm_u16_f16 (float16x4_t a) {
> + return vcvtm_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtmq_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtmu.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +uint16x8_t test_vcvtmq_u16_f16 (float16x8_t a) {
> + return vcvtmq_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtn_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvtn_s16_f16 (float16x4_t a) {
> + return vcvtn_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtnq_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtns.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtnq_s16_f16 (float16x8_t a) {
> + return vcvtnq_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtn_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +uint16x4_t test_vcvtn_u16_f16 (float16x4_t a) {
> + return vcvtn_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtnq_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtnu.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +uint16x8_t test_vcvtnq_u16_f16 (float16x8_t a) {
> + return vcvtnq_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtp_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +int16x4_t test_vcvtp_s16_f16 (float16x4_t a) {
> + return vcvtp_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtpq_s16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtps.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +int16x8_t test_vcvtpq_s16_f16 (float16x8_t a) {
> + return vcvtpq_s16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtp_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x i16> [[VCVT]]
> +uint16x4_t test_vcvtp_u16_f16 (float16x4_t a) {
> + return vcvtp_u16_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vcvtpq_u16_f16
> +// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtpu.v8i16.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x i16> [[VCVT]]
> +uint16x8_t test_vcvtpq_u16_f16 (float16x8_t a) {
> + return vcvtpq_u16_f16(a);
> +}
> +
> +// FIXME: Fix the zero constant when fp16 non-storage-only type becomes available.
> +// CHECK-LABEL: test_vneg_f16
> +// CHECK: [[NEG:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a
> +// CHECK: ret <4 x half> [[NEG]]
> +float16x4_t test_vneg_f16(float16x4_t a) {
> + return vneg_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vnegq_f16
> +// CHECK: [[NEG:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a
> +// CHECK: ret <8 x half> [[NEG]]
> +float16x8_t test_vnegq_f16(float16x8_t a) {
> + return vnegq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrecpe_f16
> +// CHECK: [[RCP:%.*]] = call <4 x half> @llvm.aarch64.neon.frecpe.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RCP]]
> +float16x4_t test_vrecpe_f16(float16x4_t a) {
> + return vrecpe_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrecpeq_f16
> +// CHECK: [[RCP:%.*]] = call <8 x half> @llvm.aarch64.neon.frecpe.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RCP]]
> +float16x8_t test_vrecpeq_f16(float16x8_t a) {
> + return vrecpeq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrnd_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.trunc.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrnd_f16(float16x4_t a) {
> + return vrnd_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndq_f16(float16x8_t a) {
> + return vrndq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrnda_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.round.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrnda_f16(float16x4_t a) {
> + return vrnda_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndaq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.round.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndaq_f16(float16x8_t a) {
> + return vrndaq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndi_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrndi_f16(float16x4_t a) {
> + return vrndi_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndiq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndiq_f16(float16x8_t a) {
> + return vrndiq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndm_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.floor.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrndm_f16(float16x4_t a) {
> + return vrndm_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndmq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndmq_f16(float16x8_t a) {
> + return vrndmq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndn_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.aarch64.neon.frintn.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrndn_f16(float16x4_t a) {
> + return vrndn_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndnq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.aarch64.neon.frintn.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndnq_f16(float16x8_t a) {
> + return vrndnq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndp_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.ceil.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrndp_f16(float16x4_t a) {
> + return vrndp_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndpq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndpq_f16(float16x8_t a) {
> + return vrndpq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndx_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.rint.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrndx_f16(float16x4_t a) {
> + return vrndx_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrndxq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.rint.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrndxq_f16(float16x8_t a) {
> + return vrndxq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrsqrte_f16
> +// CHECK: [[RND:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrte.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[RND]]
> +float16x4_t test_vrsqrte_f16(float16x4_t a) {
> + return vrsqrte_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vrsqrteq_f16
> +// CHECK: [[RND:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrte.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[RND]]
> +float16x8_t test_vrsqrteq_f16(float16x8_t a) {
> + return vrsqrteq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vsqrt_f16
> +// CHECK: [[SQR:%.*]] = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)
> +// CHECK: ret <4 x half> [[SQR]]
> +float16x4_t test_vsqrt_f16(float16x4_t a) {
> + return vsqrt_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vsqrtq_f16
> +// CHECK: [[SQR:%.*]] = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)
> +// CHECK: ret <8 x half> [[SQR]]
> +float16x8_t test_vsqrtq_f16(float16x8_t a) {
> + return vsqrtq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vadd_f16
> +// CHECK: [[ADD:%.*]] = fadd <4 x half> %a, %b
> +// CHECK: ret <4 x half> [[ADD]]
> +float16x4_t test_vadd_f16(float16x4_t a, float16x4_t b) {
> + return vadd_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vaddq_f16
> +// CHECK: [[ADD:%.*]] = fadd <8 x half> %a, %b
> +// CHECK: ret <8 x half> [[ADD]]
> +float16x8_t test_vaddq_f16(float16x8_t a, float16x8_t b) {
> + return vaddq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vabd_f16
> +// CHECK: [[ABD:%.*]] = call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[ABD]]
> +float16x4_t test_vabd_f16(float16x4_t a, float16x4_t b) {
> + return vabd_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vabdq_f16
> +// CHECK: [[ABD:%.*]] = call <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[ABD]]
> +float16x8_t test_vabdq_f16(float16x8_t a, float16x8_t b) {
> + return vabdq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcage_f16
> +// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x i16> [[ABS]]
> +uint16x4_t test_vcage_f16(float16x4_t a, float16x4_t b) {
> + return vcage_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcageq_f16
> +// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x i16> [[ABS]]
> +uint16x8_t test_vcageq_f16(float16x8_t a, float16x8_t b) {
> + return vcageq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcagt_f16
> +// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x i16> [[ABS]]
> +uint16x4_t test_vcagt_f16(float16x4_t a, float16x4_t b) {
> + return vcagt_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcagtq_f16
> +// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x i16> [[ABS]]
> +uint16x8_t test_vcagtq_f16(float16x8_t a, float16x8_t b) {
> + return vcagtq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcale_f16
> +// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
> +// CHECK: ret <4 x i16> [[ABS]]
> +uint16x4_t test_vcale_f16(float16x4_t a, float16x4_t b) {
> + return vcale_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcaleq_f16
> +// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
> +// CHECK: ret <8 x i16> [[ABS]]
> +uint16x8_t test_vcaleq_f16(float16x8_t a, float16x8_t b) {
> + return vcaleq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcalt_f16
> +// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a)
> +// CHECK: ret <4 x i16> [[ABS]]
> +uint16x4_t test_vcalt_f16(float16x4_t a, float16x4_t b) {
> + return vcalt_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcaltq_f16
> +// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a)
> +// CHECK: ret <8 x i16> [[ABS]]
> +uint16x8_t test_vcaltq_f16(float16x8_t a, float16x8_t b) {
> + return vcaltq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vceq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oeq <4 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vceq_f16(float16x4_t a, float16x4_t b) {
> + return vceq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vceqq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oeq <8 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vceqq_f16(float16x8_t a, float16x8_t b) {
> + return vceqq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcge_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oge <4 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcge_f16(float16x4_t a, float16x4_t b) {
> + return vcge_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcgeq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp oge <8 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcgeq_f16(float16x8_t a, float16x8_t b) {
> + return vcgeq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcgt_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ogt <4 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcgt_f16(float16x4_t a, float16x4_t b) {
> + return vcgt_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcgtq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ogt <8 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcgtq_f16(float16x8_t a, float16x8_t b) {
> + return vcgtq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcle_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ole <4 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vcle_f16(float16x4_t a, float16x4_t b) {
> + return vcle_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcleq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp ole <8 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcleq_f16(float16x8_t a, float16x8_t b) {
> + return vcleq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vclt_f16
> +// CHECK: [[TMP1:%.*]] = fcmp olt <4 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
> +// CHECK: ret <4 x i16> [[TMP2]]
> +uint16x4_t test_vclt_f16(float16x4_t a, float16x4_t b) {
> + return vclt_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcltq_f16
> +// CHECK: [[TMP1:%.*]] = fcmp olt <8 x half> %a, %b
> +// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16>
> +// CHECK: ret <8 x i16> [[TMP2]]
> +uint16x8_t test_vcltq_f16(float16x8_t a, float16x8_t b) {
> + return vcltq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vcvt_n_f16_s16
> +// CHECK: [[CVT:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16> %vcvt_n, i32 2)
> +// CHECK: ret <4 x half> [[CVT]]
> +float16x4_t test_vcvt_n_f16_s16(int16x4_t a) {
> + return vcvt_n_f16_s16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_n_f16_s16
> +// CHECK: [[CVT:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16> %vcvt_n, i32 2)
> +// CHECK: ret <8 x half> [[CVT]]
> +float16x8_t test_vcvtq_n_f16_s16(int16x8_t a) {
> + return vcvtq_n_f16_s16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvt_n_f16_u16
> +// CHECK: [[CVT:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16> %vcvt_n, i32 2)
> +// CHECK: ret <4 x half> [[CVT]]
> +float16x4_t test_vcvt_n_f16_u16(uint16x4_t a) {
> + return vcvt_n_f16_u16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_n_f16_u16
> +// CHECK: [[CVT:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16> %vcvt_n, i32 2)
> +// CHECK: ret <8 x half> [[CVT]]
> +float16x8_t test_vcvtq_n_f16_u16(uint16x8_t a) {
> + return vcvtq_n_f16_u16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvt_n_s16_f16
> +// CHECK: [[CVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half> %vcvt_n, i32 2)
> +// CHECK: ret <4 x i16> [[CVT]]
> +int16x4_t test_vcvt_n_s16_f16(float16x4_t a) {
> + return vcvt_n_s16_f16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_n_s16_f16
> +// CHECK: [[CVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half> %vcvt_n, i32 2)
> +// CHECK: ret <8 x i16> [[CVT]]
> +int16x8_t test_vcvtq_n_s16_f16(float16x8_t a) {
> + return vcvtq_n_s16_f16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvt_n_u16_f16
> +// CHECK: [[CVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half> %vcvt_n, i32 2)
> +// CHECK: ret <4 x i16> [[CVT]]
> +uint16x4_t test_vcvt_n_u16_f16(float16x4_t a) {
> + return vcvt_n_u16_f16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vcvtq_n_u16_f16
> +// CHECK: [[CVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half> %vcvt_n, i32 2)
> +// CHECK: ret <8 x i16> [[CVT]]
> +uint16x8_t test_vcvtq_n_u16_f16(float16x8_t a) {
> + return vcvtq_n_u16_f16(a, 2);
> +}
> +
> +// CHECK-LABEL: test_vdiv_f16
> +// CHECK: [[DIV:%.*]] = fdiv <4 x half> %a, %b
> +// CHECK: ret <4 x half> [[DIV]]
> +float16x4_t test_vdiv_f16(float16x4_t a, float16x4_t b) {
> + return vdiv_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vdivq_f16
> +// CHECK: [[DIV:%.*]] = fdiv <8 x half> %a, %b
> +// CHECK: ret <8 x half> [[DIV]]
> +float16x8_t test_vdivq_f16(float16x8_t a, float16x8_t b) {
> + return vdivq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmax_f16
> +// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmax.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MAX]]
> +float16x4_t test_vmax_f16(float16x4_t a, float16x4_t b) {
> + return vmax_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmaxq_f16
> +// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmax.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MAX]]
> +float16x8_t test_vmaxq_f16(float16x8_t a, float16x8_t b) {
> + return vmaxq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmaxnm_f16
> +// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MAX]]
> +float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
> + return vmaxnm_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmaxnmq_f16
> +// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnm.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MAX]]
> +float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
> + return vmaxnmq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmin_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fmin.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vmin_f16(float16x4_t a, float16x4_t b) {
> + return vmin_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vminq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fmin.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vminq_f16(float16x8_t a, float16x8_t b) {
> + return vminq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vminnm_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
> + return vminnm_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vminnmq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnm.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
> + return vminnmq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmul_f16
> +// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, %b
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmul_f16(float16x4_t a, float16x4_t b) {
> + return vmul_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmulq_f16
> +// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, %b
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulq_f16(float16x8_t a, float16x8_t b) {
> + return vmulq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmulx_f16
> +// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmulx_f16(float16x4_t a, float16x4_t b) {
> + return vmulx_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmulxq_f16
> +// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulxq_f16(float16x8_t a, float16x8_t b) {
> + return vmulxq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpadd_f16
> +// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.aarch64.neon.addp.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[ADD]]
> +float16x4_t test_vpadd_f16(float16x4_t a, float16x4_t b) {
> + return vpadd_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpaddq_f16
> +// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.aarch64.neon.addp.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[ADD]]
> +float16x8_t test_vpaddq_f16(float16x8_t a, float16x8_t b) {
> + return vpaddq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpmax_f16
> +// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxp.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MAX]]
> +float16x4_t test_vpmax_f16(float16x4_t a, float16x4_t b) {
> + return vpmax_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpmaxq_f16
> +// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxp.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MAX]]
> +float16x8_t test_vpmaxq_f16(float16x8_t a, float16x8_t b) {
> + return vpmaxq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpmaxnm_f16
> +// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MAX]]
> +float16x4_t test_vpmaxnm_f16(float16x4_t a, float16x4_t b) {
> + return vpmaxnm_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpmaxnmq_f16
> +// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MAX]]
> +float16x8_t test_vpmaxnmq_f16(float16x8_t a, float16x8_t b) {
> + return vpmaxnmq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpmin_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminp.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vpmin_f16(float16x4_t a, float16x4_t b) {
> + return vpmin_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpminq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminp.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vpminq_f16(float16x8_t a, float16x8_t b) {
> + return vpminq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpminnm_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vpminnm_f16(float16x4_t a, float16x4_t b) {
> + return vpminnm_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vpminnmq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vpminnmq_f16(float16x8_t a, float16x8_t b) {
> + return vpminnmq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vrecps_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.frecps.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vrecps_f16(float16x4_t a, float16x4_t b) {
> + return vrecps_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vrecpsq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.frecps.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vrecpsq_f16(float16x8_t a, float16x8_t b) {
> + return vrecpsq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vrsqrts_f16
> +// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrts.v4f16(<4 x half> %a, <4 x half> %b)
> +// CHECK: ret <4 x half> [[MIN]]
> +float16x4_t test_vrsqrts_f16(float16x4_t a, float16x4_t b) {
> + return vrsqrts_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vrsqrtsq_f16
> +// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrts.v8f16(<8 x half> %a, <8 x half> %b)
> +// CHECK: ret <8 x half> [[MIN]]
> +float16x8_t test_vrsqrtsq_f16(float16x8_t a, float16x8_t b) {
> + return vrsqrtsq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vsub_f16
> +// CHECK: [[ADD:%.*]] = fsub <4 x half> %a, %b
> +// CHECK: ret <4 x half> [[ADD]]
> +float16x4_t test_vsub_f16(float16x4_t a, float16x4_t b) {
> + return vsub_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vsubq_f16
> +// CHECK: [[ADD:%.*]] = fsub <8 x half> %a, %b
> +// CHECK: ret <8 x half> [[ADD]]
> +float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b) {
> + return vsubq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vfma_f16
> +// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)
> +// CHECK: ret <4 x half> [[ADD]]
> +float16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
> + return vfma_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmaq_f16
> +// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)
> +// CHECK: ret <8 x half> [[ADD]]
> +float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
> + return vfmaq_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfms_f16
> +// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a)
> +// CHECK: ret <4 x half> [[ADD]]
> +float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
> + return vfms_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmsq_f16
> +// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a)
> +// CHECK: ret <8 x half> [[ADD]]
> +float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
> + return vfmsq_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfma_lane_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])
> +// CHECK: ret <4 x half> [[FMLA]]
> +float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
> + return vfma_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfmaq_lane_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])
> +// CHECK: ret <8 x half> [[FMLA]]
> +float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {
> + return vfmaq_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfma_laneq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
> +// CHECK: ret <4 x half> [[FMLA]]
> +float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
> + return vfma_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vfmaq_laneq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])
> +// CHECK: ret <8 x half> [[FMLA]]
> +float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
> + return vfmaq_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vfma_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3
> +// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> [[TMP3]], <4 x half> %a)
> +// CHECK: ret <4 x half> [[FMA]]
> +float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) {
> + return vfma_n_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmaq_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7
> +// CHECK: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> [[TMP7]], <8 x half> %a)
> +// CHECK: ret <8 x half> [[FMA]]
> +float16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {
> + return vfmaq_n_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmah_lane_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[EXTR:%.*]] = extractelement <4 x half> [[TMP1]], i32 3
> +// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)
> +// CHECK: ret half [[FMA]]
> +float16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) {
> + return vfmah_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfmah_laneq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[EXTR:%.*]] = extractelement <8 x half> [[TMP1]], i32 7
> +// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)
> +// CHECK: ret half [[FMA]]
> +float16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) {
> + return vfmah_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vfms_lane_f16
> +// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])
> +// CHECK: ret <4 x half> [[FMA]]
> +float16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {
> + return vfms_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfmsq_lane_f16
> +// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])
> +// CHECK: ret <8 x half> [[FMLA]]
> +float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {
> + return vfmsq_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfms_laneq_f16
> +// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])
> +// CHECK: ret <4 x half> [[FMLA]]
> +float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {
> + return vfms_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vfmsq_laneq_f16
> +// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
> +// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])
> +// CHECK: ret <8 x half> [[FMLA]]
> +float16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {
> + return vfmsq_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vfms_n_f16
> +// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3
> +// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> [[TMP3]], <4 x half> %a)
> +// CHECK: ret <4 x half> [[FMA]]
> +float16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) {
> + return vfms_n_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmsq_n_f16
> +// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7
> +// CHECK: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> [[TMP7]], <8 x half> %a)
> +// CHECK: ret <8 x half> [[FMA]]
> +float16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {
> + return vfmsq_n_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vfmsh_lane_f16
> +// CHECK: [[TMP0:%.*]] = fpext half %b to float
> +// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]]
> +// CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>
> +// CHECK: [[EXTR:%.*]] = extractelement <4 x half> [[TMP3]], i32 3
> +// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)
> +// CHECK: ret half [[FMA]]
> +float16_t test_vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t c) {
> + return vfmsh_lane_f16(a, b, c, 3);
> +}
> +
> +// CHECK-LABEL: test_vfmsh_laneq_f16
> +// CHECK: [[TMP0:%.*]] = fpext half %b to float
> +// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]]
> +// CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>
> +// CHECK: [[EXTR:%.*]] = extractelement <8 x half> [[TMP3]], i32 7
> +// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)
> +// CHECK: ret half [[FMA]]
> +float16_t test_vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t c) {
> + return vfmsh_laneq_f16(a, b, c, 7);
> +}
> +
> +// CHECK-LABEL: test_vmul_lane_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP0]]
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmul_lane_f16(float16x4_t a, float16x4_t b) {
> + return vmul_lane_f16(a, b, 3);
> +}
> +
> +// CHECK-LABEL: test_vmulq_lane_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP0]]
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulq_lane_f16(float16x8_t a, float16x4_t b) {
> + return vmulq_lane_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmul_laneq_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP0]]
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmul_laneq_f16(float16x4_t a, float16x8_t b) {
> + return vmul_laneq_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmulq_laneq_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP0]]
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulq_laneq_f16(float16x8_t a, float16x8_t b) {
> + return vmulq_laneq_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmul_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %b, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %b, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %b, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %b, i32 3
> +// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP3]]
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmul_n_f16(float16x4_t a, float16_t b) {
> + return vmul_n_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmulq_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %b, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %b, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %b, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %b, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %b, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %b, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %b, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %b, i32 7
> +// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP7]]
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulq_n_f16(float16x8_t a, float16_t b) {
> + return vmulq_n_f16(a, b);
> +}
> +
> +// FIXME: Fix it when fp16 non-storage-only type becomes available.
> +// CHECK-LABEL: test_vmulh_lane_f16
> +// CHECK: [[CONV0:%.*]] = fpext half %a to float
> +// CHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float
> +// CHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]
> +// CHECK: [[CONV3:%.*]] = fptrunc float %mul to half
> +// CHECK: ret half [[CONV3:%.*]]
> +float16_t test_vmulh_lane_f16(float16_t a, float16x4_t b) {
> + return vmulh_lane_f16(a, b, 3);
> +}
> +
> +// CHECK-LABEL: test_vmulh_laneq_f16
> +// CHECK: [[CONV0:%.*]] = fpext half %a to float
> +// CHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float
> +// CHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]
> +// CHECK: [[CONV3:%.*]] = fptrunc float %mul to half
> +// CHECK: ret half [[CONV3:%.*]]
> +float16_t test_vmulh_laneq_f16(float16_t a, float16x8_t b) {
> + return vmulh_laneq_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmulx_lane_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP0]])
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmulx_lane_f16(float16x4_t a, float16x4_t b) {
> + return vmulx_lane_f16(a, b, 3);
> +}
> +
> +// CHECK-LABEL: test_vmulxq_lane_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP0]])
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulxq_lane_f16(float16x8_t a, float16x4_t b) {
> + return vmulxq_lane_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmulx_laneq_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP0]])
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmulx_laneq_f16(float16x4_t a, float16x8_t b) {
> + return vmulx_laneq_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmulxq_laneq_f16
> +// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP0]])
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulxq_laneq_f16(float16x8_t a, float16x8_t b) {
> + return vmulxq_laneq_f16(a, b, 7);
> +}
> +
> +// CHECK-LABEL: test_vmulx_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %b, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %b, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %b, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %b, i32 3
> +// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP3]])
> +// CHECK: ret <4 x half> [[MUL]]
> +float16x4_t test_vmulx_n_f16(float16x4_t a, float16_t b) {
> + return vmulx_n_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmulxq_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %b, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %b, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %b, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %b, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %b, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %b, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %b, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %b, i32 7
> +// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP7]])
> +// CHECK: ret <8 x half> [[MUL]]
> +float16x8_t test_vmulxq_n_f16(float16x8_t a, float16_t b) {
> + return vmulxq_n_f16(a, b);
> +}
> +
> +/* TODO: Not implemented yet (needs scalar intrinsic from arm_fp16.h)
> +// CCHECK-LABEL: test_vmulxh_lane_f16
> +// CCHECK: [[CONV0:%.*]] = fpext half %a to float
> +// CCHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float
> +// CCHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]
> +// CCHECK: [[CONV3:%.*]] = fptrunc float %mul to half
> +// CCHECK: ret half [[CONV3:%.*]]
> +float16_t test_vmulxh_lane_f16(float16_t a, float16x4_t b) {
> + return vmulxh_lane_f16(a, b, 3);
> +}
> +
> +// CCHECK-LABEL: test_vmulxh_laneq_f16
> +// CCHECK: [[CONV0:%.*]] = fpext half %a to float
> +// CCHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float
> +// CCHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]
> +// CCHECK: [[CONV3:%.*]] = fptrunc float %mul to half
> +// CCHECK: ret half [[CONV3:%.*]]
> +float16_t test_vmulxh_laneq_f16(float16_t a, float16x8_t b) {
> + return vmulxh_laneq_f16(a, b, 7);
> +}
> +*/
> +
> +// CHECK-LABEL: test_vmaxv_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vmaxv_f16(float16x4_t a) {
> + return vmaxv_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vmaxvq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vmaxvq_f16(float16x8_t a) {
> + return vmaxvq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vminv_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vminv_f16(float16x4_t a) {
> + return vminv_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vminvq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v8f16(<8 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vminvq_f16(float16x8_t a) {
> + return vminvq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vmaxnmv_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v4f16(<4 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vmaxnmv_f16(float16x4_t a) {
> + return vmaxnmv_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vmaxnmvq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v8f16(<8 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vmaxnmvq_f16(float16x8_t a) {
> + return vmaxnmvq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vminnmv_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v4f16(<4 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vminnmv_f16(float16x4_t a) {
> + return vminnmv_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vminnmvq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v8f16(<8 x half> [[TMP1]])
> +// CHECK: ret half [[MAX]]
> +float16_t test_vminnmvq_f16(float16x8_t a) {
> + return vminnmvq_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vbsl_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %c to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[TMP4:%.*]] = and <4 x i16> %a, [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
> +// CHECK: [[TMP6:%.*]] = and <4 x i16> [[TMP5]], [[TMP3]]
> +// CHECK: [[TMP7:%.*]] = or <4 x i16> [[TMP4]], [[TMP6]]
> +// CHECK: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP7]] to <4 x half>
> +// CHECK: ret <4 x half> [[TMP8]]
> +float16x4_t test_vbsl_f16(uint16x4_t a, float16x4_t b, float16x4_t c) {
> + return vbsl_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vbslq_f16
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %b to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %c to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
> +// CHECK: [[TMP4:%.*]] = and <8 x i16> %a, [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
> +// CHECK: [[TMP6:%.*]] = and <8 x i16> [[TMP5]], [[TMP3]]
> +// CHECK: [[TMP7:%.*]] = or <8 x i16> [[TMP4]], [[TMP6]]
> +// CHECK: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP7]] to <8 x half>
> +// CHECK: ret <8 x half> [[TMP8]]
> +float16x8_t test_vbslq_f16(uint16x8_t a, float16x8_t b, float16x8_t c) {
> + return vbslq_f16(a, b, c);
> +}
> +
> +// CHECK-LABEL: test_vzip_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
> +// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
> +// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)
> +float16x4x2_t test_vzip_f16(float16x4_t a, float16x4_t b) {
> + return vzip_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vzipq_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
> +// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
> +// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)
> +float16x8x2_t test_vzipq_f16(float16x8_t a, float16x8_t b) {
> + return vzipq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vuzp_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
> +// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
> +// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)
> +float16x4x2_t test_vuzp_f16(float16x4_t a, float16x4_t b) {
> + return vuzp_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vuzpq_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
> +// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
> +// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)
> +float16x8x2_t test_vuzpq_f16(float16x8_t a, float16x8_t b) {
> + return vuzpq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vtrn_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
> +// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
> +// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)
> +float16x4x2_t test_vtrn_f16(float16x4_t a, float16x4_t b) {
> + return vtrn_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vtrnq_f16
> +// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16
> +// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*
> +// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
> +// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]]
> +// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1
> +// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
> +// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]
> +// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*
> +// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*
> +// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)
> +float16x8x2_t test_vtrnq_f16(float16x8_t a, float16x8_t b) {
> + return vtrnq_f16(a, b);
> +}
> +
> +// CHECK-LABEL: test_vmov_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %a, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %a, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %a, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %a, i32 3
> +// CHECK: ret <4 x half> [[TMP3]]
> +float16x4_t test_vmov_n_f16(float16_t a) {
> + return vmov_n_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vmovq_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %a, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %a, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %a, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %a, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %a, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %a, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %a, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %a, i32 7
> +// CHECK: ret <8 x half> [[TMP7]]
> +float16x8_t test_vmovq_n_f16(float16_t a) {
> + return vmovq_n_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vdup_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %a, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %a, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %a, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %a, i32 3
> +// CHECK: ret <4 x half> [[TMP3]]
> +float16x4_t test_vdup_n_f16(float16_t a) {
> + return vdup_n_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vdupq_n_f16
> +// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %a, i32 0
> +// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %a, i32 1
> +// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %a, i32 2
> +// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %a, i32 3
> +// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %a, i32 4
> +// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %a, i32 5
> +// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %a, i32 6
> +// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %a, i32 7
> +// CHECK: ret <8 x half> [[TMP7]]
> +float16x8_t test_vdupq_n_f16(float16_t a) {
> + return vdupq_n_f16(a);
> +}
> +
> +// CHECK-LABEL: test_vdup_lane_f16
> +// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: ret <4 x half> [[SHFL]]
> +float16x4_t test_vdup_lane_f16(float16x4_t a) {
> + return vdup_lane_f16(a, 3);
> +}
> +
> +// CHECK-LABEL: test_vdupq_lane_f16
> +// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: ret <8 x half> [[SHFL]]
> +float16x8_t test_vdupq_lane_f16(float16x4_t a) {
> + return vdupq_lane_f16(a, 7);
> +}
> +
> +// CHECK-LABEL: @test_vext_f16(
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
> +// CHECK: [[VEXT:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>
> +// CHECK: ret <4 x half> [[VEXT]]
> +float16x4_t test_vext_f16(float16x4_t a, float16x4_t b) {
> + return vext_f16(a, b, 2);
> +}
> +
> +// CHECK-LABEL: @test_vextq_f16(
> +// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
> +// CHECK: [[VEXT:%.*]] = shufflevector <8 x half> [[TMP2]], <8 x half> [[TMP3]], <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
> +// CHECK: ret <8 x half> [[VEXT]]
> +float16x8_t test_vextq_f16(float16x8_t a, float16x8_t b) {
> + return vextq_f16(a, b, 5);
> +}
> +
> +// CHECK-LABEL: @test_vrev64_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
> +// CHECK: ret <4 x half> [[SHFL]]
> +float16x4_t test_vrev64_f16(float16x4_t a) {
> + return vrev64_f16(a);
> +}
> +
> +// CHECK-LABEL: @test_vrev64q_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
> +// CHECK: ret <8 x half> [[SHFL]]
> +float16x8_t test_vrev64q_f16(float16x8_t a) {
> + return vrev64q_f16(a);
> +}
> +
> +// CHECK-LABEL: @test_vzip1_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
> +// CHECK: ret <4 x half> [[SHFL]]
> +float16x4_t test_vzip1_f16(float16x4_t a, float16x4_t b) {
> + return vzip1_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vzip1q_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
> +// CHECK: ret <8 x half> [[SHFL]]
> +float16x8_t test_vzip1q_f16(float16x8_t a, float16x8_t b) {
> + return vzip1q_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vzip2_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
> +// CHECK: ret <4 x half> [[SHFL]]
> +float16x4_t test_vzip2_f16(float16x4_t a, float16x4_t b) {
> + return vzip2_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vzip2q_f16(
> +// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
> +// CHECK: ret <8 x half> [[SHFL]]
> +float16x8_t test_vzip2q_f16(float16x8_t a, float16x8_t b) {
> + return vzip2q_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vuzp1_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
> +// CHECK: ret <4 x half> [[SHUFFLE_I]]
> +float16x4_t test_vuzp1_f16(float16x4_t a, float16x4_t b) {
> + return vuzp1_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vuzp1q_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
> +// CHECK: ret <8 x half> [[SHUFFLE_I]]
> +float16x8_t test_vuzp1q_f16(float16x8_t a, float16x8_t b) {
> + return vuzp1q_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vuzp2_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
> +// CHECK: ret <4 x half> [[SHUFFLE_I]]
> +float16x4_t test_vuzp2_f16(float16x4_t a, float16x4_t b) {
> + return vuzp2_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vuzp2q_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
> +// CHECK: ret <8 x half> [[SHUFFLE_I]]
> +float16x8_t test_vuzp2q_f16(float16x8_t a, float16x8_t b) {
> + return vuzp2q_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vtrn1_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
> +// CHECK: ret <4 x half> [[SHUFFLE_I]]
> +float16x4_t test_vtrn1_f16(float16x4_t a, float16x4_t b) {
> + return vtrn1_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vtrn1q_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
> +// CHECK: ret <8 x half> [[SHUFFLE_I]]
> +float16x8_t test_vtrn1q_f16(float16x8_t a, float16x8_t b) {
> + return vtrn1q_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vtrn2_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
> +// CHECK: ret <4 x half> [[SHUFFLE_I]]
> +float16x4_t test_vtrn2_f16(float16x4_t a, float16x4_t b) {
> + return vtrn2_f16(a, b);
> +}
> +
> +// CHECK-LABEL: @test_vtrn2q_f16(
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
> +// CHECK: ret <8 x half> [[SHUFFLE_I]]
> +float16x8_t test_vtrn2q_f16(float16x8_t a, float16x8_t b) {
> + return vtrn2q_f16(a, b);
> +}
> +
>
> Modified: cfe/trunk/utils/TableGen/NeonEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/NeonEmitter.cpp?rev=304493&r1=304492&r2=304493&view=diff
> ==============================================================================
> --- cfe/trunk/utils/TableGen/NeonEmitter.cpp (original)
> +++ cfe/trunk/utils/TableGen/NeonEmitter.cpp Thu Jun 1 18:22:29 2017
> @@ -860,6 +860,10 @@ void Type::applyModifier(char Mod) {
> Float = true;
> ElementBitwidth = 64;
> break;
> + case 'H':
> + Float = true;
> + ElementBitwidth = 16;
> + break;
> case 'g':
> if (AppliedQuad)
> Bitwidth /= 2;
> @@ -1006,7 +1010,7 @@ std::string Intrinsic::getInstTypeCode(T
> }
>
> static bool isFloatingPointProtoModifier(char Mod) {
> - return Mod == 'F' || Mod == 'f';
> + return Mod == 'F' || Mod == 'f' || Mod == 'H';
> }
>
> std::string Intrinsic::getBuiltinTypeStr() {
>
>
> _______________________________________________
> cfe-commits mailing list
> cfe-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
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