<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="" applecontenteditable="true">Hi Abderrazek,<div class=""><br class=""></div><div class="">This commit results in test failures on our bots:</div><div class=""><a href="http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37166/" class="">http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37166/</a></div><div class=""><br class=""></div><div class="">Could you take a look?</div><div class=""><br class=""></div><div class="">vedant</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Jun 1, 2017, at 4:22 PM, Abderrazek Zaafrani via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org" class="">cfe-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: az<br class="">Date: Thu Jun 1 18:22:29 2017<br class="">New Revision: 304493<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=304493&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=304493&view=rev</a><br class="">Log:<br class="">[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics<br class=""><br class="">Added:<br class=""> cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c<br class="">Modified:<br class=""> cfe/trunk/include/clang/Basic/arm_neon.td<br class=""> cfe/trunk/lib/Basic/Targets.cpp<br class=""> cfe/trunk/lib/CodeGen/CGBuiltin.cpp<br class=""> cfe/trunk/lib/CodeGen/CodeGenModule.cpp<br class=""> cfe/trunk/lib/CodeGen/CodeGenTypeCache.h<br class=""> cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c<br class=""> cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c<br class=""> cfe/trunk/utils/TableGen/NeonEmitter.cpp<br class=""><br class="">Modified: cfe/trunk/include/clang/Basic/arm_neon.td<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/include/clang/Basic/arm_neon.td (original)<br class="">+++ cfe/trunk/include/clang/Basic/arm_neon.td Thu Jun 1 18:22:29 2017<br class="">@@ -227,6 +227,7 @@ def OP_UNAVAILABLE : Operation {<br class=""> // u: unsigned integer (int/float args)<br class=""> // f: float (int args)<br class=""> // F: double (int args)<br class="">+// H: half (int args)<br class=""> // d: default<br class=""> // g: default, ignore 'Q' size modifier.<br class=""> // j: default, force 'Q' size modifier.<br class="">@@ -345,6 +346,7 @@ def OP_MLSLHi : Op<(call "vmlsl", $p0,<br class=""> (call "vget_high", $p2))>;<br class=""> def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>;<br class=""> def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>;<br class="">+def OP_MULX_N : Op<(call "vmulx", $p0, (dup $p1))>;<br class=""> def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>;<br class=""> def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>;<br class=""> def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>;<br class="">@@ -1661,3 +1663,186 @@ def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqr<br class=""> def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;<br class=""> def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;<br class=""> }<br class="">+<br class="">+// ARMv8.2-A FP16 intrinsics.<br class="">+let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {<br class="">+<br class="">+ // ARMv8.2-A FP16 one-operand vector intrinsics.<br class="">+<br class="">+ // Comparison<br class="">+ def CMEQH : SInst<"vceqz", "ud", "hQh">;<br class="">+ def CMGEH : SInst<"vcgez", "ud", "hQh">;<br class="">+ def CMGTH : SInst<"vcgtz", "ud", "hQh">;<br class="">+ def CMLEH : SInst<"vclez", "ud", "hQh">;<br class="">+ def CMLTH : SInst<"vcltz", "ud", "hQh">;<br class="">+<br class="">+ // Vector conversion<br class="">+ def VCVT_F16 : SInst<"vcvt_f16", "Hd", "sUsQsQUs">;<br class="">+ def VCVT_S16 : SInst<"vcvt_s16", "xd", "hQh">;<br class="">+ def VCVT_U16 : SInst<"vcvt_u16", "ud", "hQh">;<br class="">+ def VCVTA_S16 : SInst<"vcvta_s16", "xd", "hQh">;<br class="">+ def VCVTA_U16 : SInst<"vcvta_u16", "ud", "hQh">;<br class="">+ def VCVTM_S16 : SInst<"vcvtm_s16", "xd", "hQh">;<br class="">+ def VCVTM_U16 : SInst<"vcvtm_u16", "ud", "hQh">;<br class="">+ def VCVTN_S16 : SInst<"vcvtn_s16", "xd", "hQh">;<br class="">+ def VCVTN_U16 : SInst<"vcvtn_u16", "ud", "hQh">;<br class="">+ def VCVTP_S16 : SInst<"vcvtp_s16", "xd", "hQh">;<br class="">+ def VCVTP_U16 : SInst<"vcvtp_u16", "ud", "hQh">;<br class="">+<br class="">+ // Vector rounding<br class="">+ def FRINTZH : SInst<"vrnd", "dd", "hQh">;<br class="">+ def FRINTNH : SInst<"vrndn", "dd", "hQh">;<br class="">+ def FRINTAH : SInst<"vrnda", "dd", "hQh">;<br class="">+ def FRINTPH : SInst<"vrndp", "dd", "hQh">;<br class="">+ def FRINTMH : SInst<"vrndm", "dd", "hQh">;<br class="">+ def FRINTXH : SInst<"vrndx", "dd", "hQh">;<br class="">+ def FRINTIH : SInst<"vrndi", "dd", "hQh">;<br class="">+<br class="">+ // Misc.<br class="">+ def VABSH : SInst<"vabs", "dd", "hQh">;<br class="">+ def VNEGH : SOpInst<"vneg", "dd", "hQh", OP_NEG>;<br class="">+ def VRECPEH : SInst<"vrecpe", "dd", "hQh">;<br class="">+ def FRSQRTEH : SInst<"vrsqrte", "dd", "hQh">;<br class="">+ def FSQRTH : SInst<"vsqrt", "dd", "hQh">;<br class="">+<br class="">+ // ARMv8.2-A FP16 two-operands vector intrinsics.<br class="">+<br class="">+ // Misc.<br class="">+ def VADDH : SOpInst<"vadd", "ddd", "hQh", OP_ADD>;<br class="">+ def VABDH : SInst<"vabd", "ddd", "hQh">;<br class="">+ def VSUBH : SOpInst<"vsub", "ddd", "hQh", OP_SUB>;<br class="">+<br class="">+ // Comparison<br class="">+ let InstName = "vacge" in {<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span> def VCAGEH : SInst<"vcage", "udd", "hQh">;<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span> def VCALEH : SInst<"vcale", "udd", "hQh">;<br class="">+ }<br class="">+ let InstName = "vacgt" in {<br class="">+ def VCAGTH : SInst<"vcagt", "udd", "hQh">;<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span> def VCALTH : SInst<"vcalt", "udd", "hQh">;<br class="">+ }<br class="">+ def VCEQH : SOpInst<"vceq", "udd", "hQh", OP_EQ>;<br class="">+ def VCGEH : SOpInst<"vcge", "udd", "hQh", OP_GE>;<br class="">+ def VCGTH : SOpInst<"vcgt", "udd", "hQh", OP_GT>;<br class="">+ let InstName = "vcge" in<br class="">+ def VCLEH : SOpInst<"vcle", "udd", "hQh", OP_LE>;<br class="">+ let InstName = "vcgt" in<br class="">+ def VCLTH : SOpInst<"vclt", "udd", "hQh", OP_LT>;<br class="">+<br class="">+ // Vector conversion<br class="">+ let isVCVT_N = 1 in {<br class="">+ def VCVT_N_F16 : SInst<"vcvt_n_f16", "Hdi", "sUsQsQUs">;<br class="">+ def VCVT_N_S16 : SInst<"vcvt_n_s16", "xdi", "hQh">;<br class="">+ def VCVT_N_U16 : SInst<"vcvt_n_u16", "udi", "hQh">;<br class="">+ }<br class="">+<br class="">+ // Max/Min<br class="">+ def VMAXH : SInst<"vmax", "ddd", "hQh">;<br class="">+ def VMINH : SInst<"vmin", "ddd", "hQh">;<br class="">+ def FMAXNMH : SInst<"vmaxnm", "ddd", "hQh">;<br class="">+ def FMINNMH : SInst<"vminnm", "ddd", "hQh">;<br class="">+<br class="">+ // Multiplication/Division<br class="">+ def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;<br class="">+ def MULXH : SInst<"vmulx", "ddd", "hQh">;<br class="">+ def FDIVH : IOpInst<"vdiv", "ddd", "hQh", OP_DIV>;<br class="">+<br class="">+ // Pairwise addition<br class="">+ def VPADDH : SInst<"vpadd", "ddd", "hQh">;<br class="">+<br class="">+ // Pairwise Max/Min<br class="">+ def VPMAXH : SInst<"vpmax", "ddd", "hQh">;<br class="">+ def VPMINH : SInst<"vpmin", "ddd", "hQh">;<br class="">+ // Pairwise MaxNum/MinNum<br class="">+ def FMAXNMPH : SInst<"vpmaxnm", "ddd", "hQh">;<br class="">+ def FMINNMPH : SInst<"vpminnm", "ddd", "hQh">;<br class="">+<br class="">+ // Reciprocal/Sqrt<br class="">+ def VRECPSH : SInst<"vrecps", "ddd", "hQh">;<br class="">+ def VRSQRTSH : SInst<"vrsqrts", "ddd", "hQh">;<br class="">+<br class="">+ // ARMv8.2-A FP16 three-operands vector intrinsics.<br class="">+<br class="">+ // Vector fused multiply-add operations<br class="">+ def VFMAH : SInst<"vfma", "dddd", "hQh">;<br class="">+ def VFMSH : SOpInst<"vfms", "dddd", "hQh", OP_FMLS>;<br class="">+<br class="">+ // ARMv8.2-A FP16 lane vector intrinsics.<br class="">+<br class="">+ // FMA lane<br class="">+ def VFMA_LANEH : IInst<"vfma_lane", "dddgi", "hQh">;<br class="">+ def VFMA_LANEQH : IInst<"vfma_laneq", "dddji", "hQh">;<br class="">+<br class="">+ // FMA lane with scalar argument<br class="">+ def FMLA_NH : SOpInst<"vfma_n", "ddds", "hQh", OP_FMLA_N>;<br class="">+ // Scalar floating point fused multiply-add (scalar, by element)<br class="">+ def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "sssdi", "Sh">;<br class="">+ def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "sssji", "Sh">;<br class="">+<br class="">+ // FMS lane<br class="">+ def VFMS_LANEH : IOpInst<"vfms_lane", "dddgi", "hQh", OP_FMS_LN>;<br class="">+ def VFMS_LANEQH : IOpInst<"vfms_laneq", "dddji", "hQh", OP_FMS_LNQ>;<br class="">+ // FMS lane with scalar argument<br class="">+ def FMLS_NH : SOpInst<"vfms_n", "ddds", "hQh", OP_FMLS_N>;<br class="">+ // Scalar floating foint fused multiply-subtract (scalar, by element)<br class="">+ def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "sssdi", "Sh", OP_FMS_LN>;<br class="">+ def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "sssji", "Sh", OP_FMS_LNQ>;<br class="">+<br class="">+ // Mul lane<br class="">+ def VMUL_LANEH : IOpInst<"vmul_lane", "ddgi", "hQh", OP_MUL_LN>;<br class="">+ def VMUL_LANEQH : IOpInst<"vmul_laneq", "ddji", "hQh", OP_MUL_LN>;<br class="">+ def VMUL_NH : IOpInst<"vmul_n", "dds", "hQh", OP_MUL_N>;<br class="">+ // Scalar floating point multiply (scalar, by element)<br class="">+ def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "ssdi", "Sh", OP_SCALAR_MUL_LN>;<br class="">+ def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "ssji", "Sh", OP_SCALAR_MUL_LN>;<br class="">+<br class="">+ // Mulx lane<br class="">+ def VMULX_LANEH : IOpInst<"vmulx_lane", "ddgi", "hQh", OP_MULX_LN>;<br class="">+ def VMULX_LANEQH : IOpInst<"vmulx_laneq", "ddji", "hQh", OP_MULX_LN>;<br class="">+ def VMULX_NH : IOpInst<"vmulx_n", "dds", "hQh", OP_MULX_N>;<br class="">+ // TODO: Scalar floating point multiply extended (scalar, by element)<br class="">+ // Below ones are commented out because they need vmulx_f16(float16_t, float16_t)<br class="">+ // which will be implemented later with fp16 scalar intrinsic (arm_fp16.h)<br class="">+ //def SCALAR_FMULX_LANEH : IOpInst<"vmulx_lane", "ssdi", "Sh", OP_SCALAR_MUL_LN>;<br class="">+ //def SCALAR_FMULX_LANEQH : IOpInst<"vmulx_laneq", "ssji", "Sh", OP_SCALAR_MUL_LN>;<br class="">+<br class="">+ // ARMv8.2-A FP16 reduction vector intrinsics.<br class="">+ def VMAXVH : SInst<"vmaxv", "sd", "hQh">;<br class="">+ def VMINVH : SInst<"vminv", "sd", "hQh">;<br class="">+ def FMAXNMVH : SInst<"vmaxnmv", "sd", "hQh">;<br class="">+ def FMINNMVH : SInst<"vminnmv", "sd", "hQh">;<br class="">+<br class="">+ // Data processing intrinsics - section 5<br class="">+<br class="">+ // Logical operations<br class="">+ let isHiddenLInst = 1 in<br class="">+ def VBSLH : SInst<"vbsl", "dudd", "hQh">;<br class="">+<br class="">+ // Transposition operations<br class="">+ def VZIPH : WInst<"vzip", "2dd", "hQh">;<br class="">+ def VUZPH : WInst<"vuzp", "2dd", "hQh">;<br class="">+ def VTRNH : WInst<"vtrn", "2dd", "hQh">;<br class="">+<br class="">+ // Set all lanes to same value.<br class="">+ /* Already implemented prior to ARMv8.2-A.<br class="">+ def VMOV_NH : WOpInst<"vmov_n", "ds", "hQh", OP_DUP>;<br class="">+ def VDUP_NH : WOpInst<"vdup_n", "ds", "hQh", OP_DUP>;<br class="">+ def VDUP_LANE1H : WOpInst<"vdup_lane", "dgi", "hQh", OP_DUP_LN>;*/<br class="">+<br class="">+ // Vector Extract<br class="">+ def VEXTH : WInst<"vext", "dddi", "hQh">;<br class="">+<br class="">+ // Reverse vector elements<br class="">+ def VREV64H : WOpInst<"vrev64", "dd", "hQh", OP_REV64>;<br class="">+<br class="">+ // Permutation<br class="">+ def VTRN1H : SOpInst<"vtrn1", "ddd", "hQh", OP_TRN1>;<br class="">+ def VZIP1H : SOpInst<"vzip1", "ddd", "hQh", OP_ZIP1>;<br class="">+ def VUZP1H : SOpInst<"vuzp1", "ddd", "hQh", OP_UZP1>;<br class="">+ def VTRN2H : SOpInst<"vtrn2", "ddd", "hQh", OP_TRN2>;<br class="">+ def VZIP2H : SOpInst<"vzip2", "ddd", "hQh", OP_ZIP2>;<br class="">+ def VUZP2H : SOpInst<"vuzp2", "ddd", "hQh", OP_UZP2>;<br class="">+<br class="">+ def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "sdi", "Sh">;<br class="">+ def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "sji", "Sh">;<br class="">+}<br class=""><br class="">Modified: cfe/trunk/lib/Basic/Targets.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/lib/Basic/Targets.cpp (original)<br class="">+++ cfe/trunk/lib/Basic/Targets.cpp Thu Jun 1 18:22:29 2017<br class="">@@ -6151,6 +6151,8 @@ class AArch64TargetInfo : public TargetI<br class=""> unsigned Crypto;<br class=""> unsigned Unaligned;<br class=""> unsigned V8_1A;<br class="">+ unsigned V8_2A;<br class="">+ unsigned HasFP16;<br class=""><br class=""> static const Builtin::Info BuiltinInfo[];<br class=""><br class="">@@ -6282,6 +6284,8 @@ public:<br class=""><br class=""> if (V8_1A)<br class=""> Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");<br class="">+ if (V8_2A && FPU == NeonMode && HasFP16)<br class="">+ Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1");<br class=""><br class=""> // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.<br class=""> Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");<br class="">@@ -6309,6 +6313,8 @@ public:<br class=""> Crypto = 0;<br class=""> Unaligned = 1;<br class=""> V8_1A = 0;<br class="">+ V8_2A = 0;<br class="">+ HasFP16 = 0;<br class=""><br class=""> for (const auto &Feature : Features) {<br class=""> if (Feature == "+neon")<br class="">@@ -6321,6 +6327,10 @@ public:<br class=""> Unaligned = 0;<br class=""> if (Feature == "+v8.1a")<br class=""> V8_1A = 1;<br class="">+ if (Feature == "+v8.2a")<br class="">+ V8_2A = 1;<br class="">+ if (Feature == "+fp16")<br class="">+ HasFP16 = 1;<br class=""> }<br class=""><br class=""> setDataLayout();<br class=""><br class="">Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)<br class="">+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Jun 1 18:22:29 2017<br class="">@@ -2955,8 +2955,9 @@ static llvm::VectorType *GetNeonType(Cod<br class=""> return llvm::VectorType::get(CGF->Int8Ty, V1Ty ? 1 : (8 << IsQuad));<br class=""> case NeonTypeFlags::Int16:<br class=""> case NeonTypeFlags::Poly16:<br class="">- case NeonTypeFlags::Float16:<br class=""> return llvm::VectorType::get(CGF->Int16Ty, V1Ty ? 1 : (4 << IsQuad));<br class="">+ case NeonTypeFlags::Float16:<br class="">+ return llvm::VectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad));<br class=""> case NeonTypeFlags::Int32:<br class=""> return llvm::VectorType::get(CGF->Int32Ty, V1Ty ? 1 : (2 << IsQuad));<br class=""> case NeonTypeFlags::Int64:<br class="">@@ -2979,6 +2980,8 @@ static llvm::VectorType *GetFloatNeonTyp<br class=""> NeonTypeFlags IntTypeFlags) {<br class=""> int IsQuad = IntTypeFlags.isQuad();<br class=""> switch (IntTypeFlags.getEltType()) {<br class="">+ case NeonTypeFlags::Int16:<br class="">+ return llvm::VectorType::get(CGF->HalfTy, (4 << IsQuad));<br class=""> case NeonTypeFlags::Int32:<br class=""> return llvm::VectorType::get(CGF->FloatTy, (2 << IsQuad));<br class=""> case NeonTypeFlags::Int64:<br class="">@@ -3126,55 +3129,80 @@ static const NeonIntrinsicInfo ARMSIMDIn<br class=""> NEONMAP1(vcvt_f16_f32, arm_neon_vcvtfp2hf, 0),<br class=""> NEONMAP1(vcvt_f32_f16, arm_neon_vcvthf2fp, 0),<br class=""> NEONMAP0(vcvt_f32_v),<br class="">+ NEONMAP2(vcvt_n_f16_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvt_n_f32_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),<br class="">+ NEONMAP1(vcvt_n_s16_v, arm_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvt_n_s32_v, arm_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvt_n_s64_v, arm_neon_vcvtfp2fxs, 0),<br class="">+ NEONMAP1(vcvt_n_u16_v, arm_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvt_n_u32_v, arm_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvt_n_u64_v, arm_neon_vcvtfp2fxu, 0),<br class="">+ NEONMAP0(vcvt_s16_v),<br class=""> NEONMAP0(vcvt_s32_v),<br class=""> NEONMAP0(vcvt_s64_v),<br class="">+ NEONMAP0(vcvt_u16_v),<br class=""> NEONMAP0(vcvt_u32_v),<br class=""> NEONMAP0(vcvt_u64_v),<br class="">+ NEONMAP1(vcvta_s16_v, arm_neon_vcvtas, 0),<br class=""> NEONMAP1(vcvta_s32_v, arm_neon_vcvtas, 0),<br class=""> NEONMAP1(vcvta_s64_v, arm_neon_vcvtas, 0),<br class=""> NEONMAP1(vcvta_u32_v, arm_neon_vcvtau, 0),<br class=""> NEONMAP1(vcvta_u64_v, arm_neon_vcvtau, 0),<br class="">+ NEONMAP1(vcvtaq_s16_v, arm_neon_vcvtas, 0),<br class=""> NEONMAP1(vcvtaq_s32_v, arm_neon_vcvtas, 0),<br class=""> NEONMAP1(vcvtaq_s64_v, arm_neon_vcvtas, 0),<br class="">+ NEONMAP1(vcvtaq_u16_v, arm_neon_vcvtau, 0),<br class=""> NEONMAP1(vcvtaq_u32_v, arm_neon_vcvtau, 0),<br class=""> NEONMAP1(vcvtaq_u64_v, arm_neon_vcvtau, 0),<br class="">+ NEONMAP1(vcvtm_s16_v, arm_neon_vcvtms, 0),<br class=""> NEONMAP1(vcvtm_s32_v, arm_neon_vcvtms, 0),<br class=""> NEONMAP1(vcvtm_s64_v, arm_neon_vcvtms, 0),<br class="">+ NEONMAP1(vcvtm_u16_v, arm_neon_vcvtmu, 0),<br class=""> NEONMAP1(vcvtm_u32_v, arm_neon_vcvtmu, 0),<br class=""> NEONMAP1(vcvtm_u64_v, arm_neon_vcvtmu, 0),<br class="">+ NEONMAP1(vcvtmq_s16_v, arm_neon_vcvtms, 0),<br class=""> NEONMAP1(vcvtmq_s32_v, arm_neon_vcvtms, 0),<br class=""> NEONMAP1(vcvtmq_s64_v, arm_neon_vcvtms, 0),<br class="">+ NEONMAP1(vcvtmq_u16_v, arm_neon_vcvtmu, 0),<br class=""> NEONMAP1(vcvtmq_u32_v, arm_neon_vcvtmu, 0),<br class=""> NEONMAP1(vcvtmq_u64_v, arm_neon_vcvtmu, 0),<br class="">+ NEONMAP1(vcvtn_s16_v, arm_neon_vcvtns, 0),<br class=""> NEONMAP1(vcvtn_s32_v, arm_neon_vcvtns, 0),<br class=""> NEONMAP1(vcvtn_s64_v, arm_neon_vcvtns, 0),<br class="">+ NEONMAP1(vcvtn_u16_v, arm_neon_vcvtnu, 0),<br class=""> NEONMAP1(vcvtn_u32_v, arm_neon_vcvtnu, 0),<br class=""> NEONMAP1(vcvtn_u64_v, arm_neon_vcvtnu, 0),<br class="">+ NEONMAP1(vcvtnq_s16_v, arm_neon_vcvtns, 0),<br class=""> NEONMAP1(vcvtnq_s32_v, arm_neon_vcvtns, 0),<br class=""> NEONMAP1(vcvtnq_s64_v, arm_neon_vcvtns, 0),<br class="">+ NEONMAP1(vcvtnq_u16_v, arm_neon_vcvtnu, 0),<br class=""> NEONMAP1(vcvtnq_u32_v, arm_neon_vcvtnu, 0),<br class=""> NEONMAP1(vcvtnq_u64_v, arm_neon_vcvtnu, 0),<br class="">+ NEONMAP1(vcvtp_s16_v, arm_neon_vcvtps, 0),<br class=""> NEONMAP1(vcvtp_s32_v, arm_neon_vcvtps, 0),<br class=""> NEONMAP1(vcvtp_s64_v, arm_neon_vcvtps, 0),<br class="">+ NEONMAP1(vcvtp_u16_v, arm_neon_vcvtpu, 0),<br class=""> NEONMAP1(vcvtp_u32_v, arm_neon_vcvtpu, 0),<br class=""> NEONMAP1(vcvtp_u64_v, arm_neon_vcvtpu, 0),<br class="">+ NEONMAP1(vcvtpq_s16_v, arm_neon_vcvtps, 0),<br class=""> NEONMAP1(vcvtpq_s32_v, arm_neon_vcvtps, 0),<br class=""> NEONMAP1(vcvtpq_s64_v, arm_neon_vcvtps, 0),<br class="">+ NEONMAP1(vcvtpq_u16_v, arm_neon_vcvtpu, 0),<br class=""> NEONMAP1(vcvtpq_u32_v, arm_neon_vcvtpu, 0),<br class=""> NEONMAP1(vcvtpq_u64_v, arm_neon_vcvtpu, 0),<br class=""> NEONMAP0(vcvtq_f32_v),<br class="">+ NEONMAP2(vcvtq_n_f16_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvtq_n_f32_v, arm_neon_vcvtfxu2fp, arm_neon_vcvtfxs2fp, 0),<br class="">+ NEONMAP1(vcvtq_n_s16_v, arm_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvtq_n_s32_v, arm_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvtq_n_s64_v, arm_neon_vcvtfp2fxs, 0),<br class="">+ NEONMAP1(vcvtq_n_u16_v, arm_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvtq_n_u32_v, arm_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvtq_n_u64_v, arm_neon_vcvtfp2fxu, 0),<br class="">+ NEONMAP0(vcvtq_s16_v),<br class=""> NEONMAP0(vcvtq_s32_v),<br class=""> NEONMAP0(vcvtq_s64_v),<br class="">+ NEONMAP0(vcvtq_u16_v),<br class=""> NEONMAP0(vcvtq_u32_v),<br class=""> NEONMAP0(vcvtq_u64_v),<br class=""> NEONMAP0(vext_v),<br class="">@@ -3337,19 +3365,27 @@ static const NeonIntrinsicInfo AArch64SI<br class=""> NEONMAP1(vcnt_v, ctpop, Add1ArgType),<br class=""> NEONMAP1(vcntq_v, ctpop, Add1ArgType),<br class=""> NEONMAP1(vcvt_f16_f32, aarch64_neon_vcvtfp2hf, 0),<br class="">+ NEONMAP0(vcvt_f16_v),<br class=""> NEONMAP1(vcvt_f32_f16, aarch64_neon_vcvthf2fp, 0),<br class=""> NEONMAP0(vcvt_f32_v),<br class="">+ NEONMAP2(vcvt_n_f16_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvt_n_f32_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvt_n_f64_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class="">+ NEONMAP1(vcvt_n_s16_v, aarch64_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvt_n_s32_v, aarch64_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvt_n_s64_v, aarch64_neon_vcvtfp2fxs, 0),<br class="">+ NEONMAP1(vcvt_n_u16_v, aarch64_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvt_n_u32_v, aarch64_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvt_n_u64_v, aarch64_neon_vcvtfp2fxu, 0),<br class="">+ NEONMAP0(vcvtq_f16_v),<br class=""> NEONMAP0(vcvtq_f32_v),<br class="">+ NEONMAP2(vcvtq_n_f16_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvtq_n_f32_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class=""> NEONMAP2(vcvtq_n_f64_v, aarch64_neon_vcvtfxu2fp, aarch64_neon_vcvtfxs2fp, 0),<br class="">+ NEONMAP1(vcvtq_n_s16_v, aarch64_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvtq_n_s32_v, aarch64_neon_vcvtfp2fxs, 0),<br class=""> NEONMAP1(vcvtq_n_s64_v, aarch64_neon_vcvtfp2fxs, 0),<br class="">+ NEONMAP1(vcvtq_n_u16_v, aarch64_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvtq_n_u32_v, aarch64_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvtq_n_u64_v, aarch64_neon_vcvtfp2fxu, 0),<br class=""> NEONMAP1(vcvtx_f32_v, aarch64_neon_fcvtxn, AddRetType | Add1ArgType),<br class="">@@ -3817,9 +3853,20 @@ Value *CodeGenFunction::EmitCommonNeonBu<br class=""> case NEON::BI__builtin_neon_vcageq_v:<br class=""> case NEON::BI__builtin_neon_vcagt_v:<br class=""> case NEON::BI__builtin_neon_vcagtq_v: {<br class="">- llvm::Type *VecFlt = llvm::VectorType::get(<br class="">- VTy->getScalarSizeInBits() == 32 ? FloatTy : DoubleTy,<br class="">- VTy->getNumElements());<br class="">+ llvm::Type *Ty;<br class="">+ switch (VTy->getScalarSizeInBits()) {<br class="">+ default: llvm_unreachable("unexpected type");<br class="">+ case 32:<br class="">+ Ty = FloatTy;<br class="">+ break;<br class="">+ case 64:<br class="">+ Ty = DoubleTy;<br class="">+ break;<br class="">+ case 16:<br class="">+ Ty = HalfTy;<br class="">+ break;<br class="">+ }<br class="">+ llvm::Type *VecFlt = llvm::VectorType::get(Ty, VTy->getNumElements());<br class=""> llvm::Type *Tys[] = { VTy, VecFlt };<br class=""> Function *F = CGM.getIntrinsic(LLVMIntrinsic, Tys);<br class=""> return EmitNeonCall(F, Ops, NameHint);<br class="">@@ -3836,8 +3883,16 @@ Value *CodeGenFunction::EmitCommonNeonBu<br class=""> Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, Quad));<br class=""> return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")<br class=""> : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");<br class="">+ case NEON::BI__builtin_neon_vcvt_f16_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_f16_v:<br class="">+ Ops[0] = Builder.CreateBitCast(Ops[0], Ty);<br class="">+ Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float16, false, Quad));<br class="">+ return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")<br class="">+ : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");<br class="">+ case NEON::BI__builtin_neon_vcvt_n_f16_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_f32_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_f64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_n_f16_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_f32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_f64_v: {<br class=""> llvm::Type *Tys[2] = { GetFloatNeonType(this, Type), Ty };<br class="">@@ -3845,11 +3900,15 @@ Value *CodeGenFunction::EmitCommonNeonBu<br class=""> Function *F = CGM.getIntrinsic(Int, Tys);<br class=""> return EmitNeonCall(F, Ops, "vcvt_n");<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvt_n_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvt_n_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvt_n_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_n_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_n_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_n_u64_v: {<br class="">@@ -3861,44 +3920,63 @@ Value *CodeGenFunction::EmitCommonNeonBu<br class=""> case NEON::BI__builtin_neon_vcvt_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvt_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvt_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvt_s16_v:<br class="">+ case NEON::BI__builtin_neon_vcvt_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_s64_v:<br class="">- case NEON::BI__builtin_neon_vcvtq_u64_v: {<br class="">+ case NEON::BI__builtin_neon_vcvtq_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_s16_v:<br class="">+ case NEON::BI__builtin_neon_vcvtq_u16_v: {<br class=""> Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));<br class=""> return Usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt")<br class=""> : Builder.CreateFPToSI(Ops[0], Ty, "vcvt");<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvta_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvta_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvta_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvta_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvta_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtaq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtaq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtn_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtn_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtnq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtnq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtp_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtp_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtpq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtpq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtm_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtm_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_u64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtmq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_s64_v:<br class="">+ case NEON::BI__builtin_neon_vcvtmq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_u64_v: {<br class=""> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };<br class="">@@ -6107,7 +6185,9 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> Ops[2] = EmitNeonSplat(Ops[2], cast<ConstantInt>(Ops[3]));<br class=""> return Builder.CreateCall(F, {Ops[2], Ops[1], Ops[0]});<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vfmah_lane_f16:<br class=""> case NEON::BI__builtin_neon_vfmas_lane_f32:<br class="">+ case NEON::BI__builtin_neon_vfmah_laneq_f16:<br class=""> case NEON::BI__builtin_neon_vfmas_laneq_f32:<br class=""> case NEON::BI__builtin_neon_vfmad_lane_f64:<br class=""> case NEON::BI__builtin_neon_vfmad_laneq_f64: {<br class="">@@ -6282,18 +6362,25 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> case NEON::BI__builtin_neon_vcvt_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvt_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvt_u64_v:<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span>case NEON::BI__builtin_neon_vcvt_s16_v:<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span>case NEON::BI__builtin_neon_vcvt_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtq_s64_v:<br class="">- case NEON::BI__builtin_neon_vcvtq_u64_v: {<br class="">+ case NEON::BI__builtin_neon_vcvtq_u64_v:<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span>case NEON::BI__builtin_neon_vcvtq_s16_v:<br class="">+<span class="Apple-tab-span" style="white-space:pre"> </span>case NEON::BI__builtin_neon_vcvtq_u16_v: {<br class=""> Ops[0] = Builder.CreateBitCast(Ops[0], GetFloatNeonType(this, Type));<br class=""> if (usgn)<br class=""> return Builder.CreateFPToUI(Ops[0], Ty);<br class=""> return Builder.CreateFPToSI(Ops[0], Ty);<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvta_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvta_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtaq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_s32_v:<br class=""> case NEON::BI__builtin_neon_vcvta_u32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtaq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvta_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvtaq_s64_v:<br class="">@@ -6303,9 +6390,13 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };<br class=""> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvta");<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvtm_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtmq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtm_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_u32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtmq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtm_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvtmq_s64_v:<br class="">@@ -6315,9 +6406,13 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };<br class=""> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvtm");<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvtn_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtnq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtn_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_u32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtnq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtn_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvtnq_s64_v:<br class="">@@ -6327,9 +6422,13 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> llvm::Type *Tys[2] = { Ty, GetFloatNeonType(this, Type) };<br class=""> return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vcvtn");<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vcvtp_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtpq_s16_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_s32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtp_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_u32_v:<br class="">+ case NEON::BI__builtin_neon_vcvtpq_u16_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_u32_v:<br class=""> case NEON::BI__builtin_neon_vcvtp_s64_v:<br class=""> case NEON::BI__builtin_neon_vcvtpq_s64_v:<br class="">@@ -6502,6 +6601,24 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");<br class=""> return Builder.CreateTrunc(Ops[0], Int16Ty);<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vmaxv_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fmaxv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 4);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vmaxvq_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fmaxv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 8);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class=""> case NEON::BI__builtin_neon_vminv_u8: {<br class=""> Int = Intrinsic::aarch64_neon_uminv;<br class=""> Ty = Int32Ty;<br class="">@@ -6574,6 +6691,60 @@ Value *CodeGenFunction::EmitAArch64Built<br class=""> Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");<br class=""> return Builder.CreateTrunc(Ops[0], Int16Ty);<br class=""> }<br class="">+ case NEON::BI__builtin_neon_vminv_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fminv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 4);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vminvq_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fminv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 8);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vmaxnmv_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fmaxnmv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 4);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxnmv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vmaxnmvq_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fmaxnmv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 8);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vmaxnmv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vminnmv_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fminnmv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 4);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminnmv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class="">+ case NEON::BI__builtin_neon_vminnmvq_f16: {<br class="">+ Int = Intrinsic::aarch64_neon_fminnmv;<br class="">+ Ty = HalfTy;<br class="">+ VTy = llvm::VectorType::get(HalfTy, 8);<br class="">+ llvm::Type *Tys[2] = { Ty, VTy };<br class="">+ Ops.push_back(EmitScalarExpr(E->getArg(0)));<br class="">+ Ops[0] = EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vminnmv");<br class="">+ return Builder.CreateTrunc(Ops[0], HalfTy);<br class="">+ }<br class=""> case NEON::BI__builtin_neon_vmul_n_f64: {<br class=""> Ops[0] = Builder.CreateBitCast(Ops[0], DoubleTy);<br class=""> Value *RHS = Builder.CreateBitCast(EmitScalarExpr(E->getArg(1)), DoubleTy);<br class=""><br class="">Modified: cfe/trunk/lib/CodeGen/CodeGenModule.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/lib/CodeGen/CodeGenModule.cpp (original)<br class="">+++ cfe/trunk/lib/CodeGen/CodeGenModule.cpp Thu Jun 1 18:22:29 2017<br class="">@@ -98,6 +98,7 @@ CodeGenModule::CodeGenModule(ASTContext<br class=""> Int16Ty = llvm::Type::getInt16Ty(LLVMContext);<br class=""> Int32Ty = llvm::Type::getInt32Ty(LLVMContext);<br class=""> Int64Ty = llvm::Type::getInt64Ty(LLVMContext);<br class="">+ HalfTy = llvm::Type::getHalfTy(LLVMContext);<br class=""> FloatTy = llvm::Type::getFloatTy(LLVMContext);<br class=""> DoubleTy = llvm::Type::getDoubleTy(LLVMContext);<br class=""> PointerWidthInBits = C.getTargetInfo().getPointerWidth(0);<br class=""><br class="">Modified: cfe/trunk/lib/CodeGen/CodeGenTypeCache.h<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenTypeCache.h?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenTypeCache.h?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/lib/CodeGen/CodeGenTypeCache.h (original)<br class="">+++ cfe/trunk/lib/CodeGen/CodeGenTypeCache.h Thu Jun 1 18:22:29 2017<br class="">@@ -36,7 +36,7 @@ struct CodeGenTypeCache {<br class=""> /// i8, i16, i32, and i64<br class=""> llvm::IntegerType *Int8Ty, *Int16Ty, *Int32Ty, *Int64Ty;<br class=""> /// float, double<br class="">- llvm::Type *FloatTy, *DoubleTy;<br class="">+ llvm::Type *HalfTy, *FloatTy, *DoubleTy;<br class=""><br class=""> /// int<br class=""> llvm::IntegerType *IntTy;<br class=""><br class="">Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)<br class="">+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Thu Jun 1 18:22:29 2017<br class="">@@ -9037,10 +9037,9 @@ int64x2_t test_vld1q_s64(int64_t const *<br class=""><br class=""> // CHECK-LABEL: @test_vld1q_f16(<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*<br class="">-// CHECK: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]<br class="">-// CHECK: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half><br class="">-// CHECK: ret <8 x half> [[TMP3]]<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*<br class="">+// CHECK: [[TMP2:%.*]] = load <8 x half>, <8 x half>* [[TMP1]]<br class="">+// CHECK: ret <8 x half> [[TMP2]]<br class=""> float16x8_t test_vld1q_f16(float16_t const *a) {<br class=""> return vld1q_f16(a);<br class=""> }<br class="">@@ -9152,10 +9151,9 @@ int64x1_t test_vld1_s64(int64_t const *a<br class=""><br class=""> // CHECK-LABEL: @test_vld1_f16(<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i16>*<br class="">-// CHECK: [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]]<br class="">-// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half><br class="">-// CHECK: ret <4 x half> [[TMP3]]<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*<br class="">+// CHECK: [[TMP2:%.*]] = load <4 x half>, <4 x half>* [[TMP1]]<br class="">+// CHECK: ret <4 x half> [[TMP2]]<br class=""> float16x4_t test_vld1_f16(float16_t const *a) {<br class=""> return vld1_f16(a);<br class=""> }<br class="">@@ -9342,10 +9340,10 @@ int64x2x2_t test_vld2q_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*<br class="">-// CHECK: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0v8i16(<8 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], { <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*<br class="">+// CHECK: [[VLD2:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half> } [[VLD2]], { <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)<br class="">@@ -9573,10 +9571,10 @@ int64x1x2_t test_vld2_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*<br class="">-// CHECK: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0v4i16(<4 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], { <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*<br class="">+// CHECK: [[VLD2:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0v4f16(<4 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half> } [[VLD2]], { <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)<br class="">@@ -9804,10 +9802,10 @@ int64x2x3_t test_vld3q_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*<br class="">-// CHECK: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0v8i16(<8 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*<br class="">+// CHECK: [[VLD3:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)<br class="">@@ -10035,10 +10033,10 @@ int64x1x3_t test_vld3_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*<br class="">-// CHECK: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0v4i16(<4 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*<br class="">+// CHECK: [[VLD3:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0v4f16(<4 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)<br class="">@@ -10266,10 +10264,10 @@ int64x2x4_t test_vld4q_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x i16>*<br class="">-// CHECK: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0v8i16(<8 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <8 x half>*<br class="">+// CHECK: [[VLD4:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)<br class="">@@ -10497,10 +10495,10 @@ int64x1x4_t test_vld4_s64(int64_t const<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x i16>*<br class="">-// CHECK: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to <4 x half>*<br class="">+// CHECK: [[VLD4:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0v4f16(<4 x half>* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)<br class="">@@ -10666,9 +10664,9 @@ void test_vst1q_s64(int64_t *a, int64x2_<br class=""> // CHECK-LABEL: @test_vst1q_f16(<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*<br class="">-// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16><br class="">-// CHECK: store <8 x i16> [[TMP3]], <8 x i16>* [[TMP2]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*<br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: store <8 x half> [[TMP3]], <8 x half>* [[TMP2]]<br class=""> // CHECK: ret void<br class=""> void test_vst1q_f16(float16_t *a, float16x8_t b) {<br class=""> vst1q_f16(a, b);<br class="">@@ -10800,9 +10798,9 @@ void test_vst1_s64(int64_t *a, int64x1_t<br class=""> // CHECK-LABEL: @test_vst1_f16(<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <4 x i16>*<br class="">-// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16><br class="">-// CHECK: store <4 x i16> [[TMP3]], <4 x i16>* [[TMP2]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*<br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: store <4 x half> [[TMP3]], <4 x half>* [[TMP2]]<br class=""> // CHECK: ret void<br class=""> void test_vst1_f16(float16_t *a, float16x4_t b) {<br class=""> vst1_f16(a, b);<br class="">@@ -11056,9 +11054,9 @@ void test_vst2q_s64(int64_t *a, int64x2x<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st2.v8i16.p0i8(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st2.v8f16.p0i8(<8 x half> [[TMP7]], <8 x half> [[TMP8]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst2q_f16(float16_t *a, float16x8x2_t b) {<br class=""> vst2q_f16(a, b);<br class="">@@ -11366,9 +11364,9 @@ void test_vst2_s64(int64_t *a, int64x1x2<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st2.v4i16.p0i8(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st2.v4f16.p0i8(<4 x half> [[TMP7]], <4 x half> [[TMP8]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst2_f16(float16_t *a, float16x4x2_t b) {<br class=""> vst2_f16(a, b);<br class="">@@ -11716,10 +11714,10 @@ void test_vst3q_s64(int64_t *a, int64x2x<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st3.v8i16.p0i8(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st3.v8f16.p0i8(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst3q_f16(float16_t *a, float16x8x3_t b) {<br class=""> vst3q_f16(a, b);<br class="">@@ -12085,10 +12083,10 @@ void test_vst3_s64(int64_t *a, int64x1x3<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st3.v4i16.p0i8(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st3.v4f16.p0i8(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst3_f16(float16_t *a, float16x4x3_t b) {<br class=""> vst3_f16(a, b);<br class="">@@ -12494,11 +12492,11 @@ void test_vst4q_s64(int64_t *a, int64x2x<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st4.v8i16.p0i8(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st4.v8f16.p0i8(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst4q_f16(float16_t *a, float16x8x4_t b) {<br class=""> vst4q_f16(a, b);<br class="">@@ -12922,11 +12920,11 @@ void test_vst4_s64(int64_t *a, int64x1x4<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st4.v4i16.p0i8(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i8* [[TMP2]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st4.v4f16.p0i8(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst4_f16(float16_t *a, float16x4x4_t b) {<br class=""> vst4_f16(a, b);<br class="">@@ -13208,10 +13206,10 @@ int64x2x2_t test_vld1q_s64_x2(int64_t co<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)<br class="">@@ -13454,10 +13452,10 @@ int64x1x2_t test_vld1_s64_x2(int64_t con<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)<br class="">@@ -13700,10 +13698,10 @@ int64x2x3_t test_vld1q_s64_x3(int64_t co<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)<br class="">@@ -13946,10 +13944,10 @@ int64x1x3_t test_vld1_s64_x3(int64_t con<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)<br class="">@@ -14192,10 +14190,10 @@ int64x2x4_t test_vld1q_s64_x4(int64_t co<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD1XN]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)<br class="">@@ -14438,10 +14436,10 @@ int64x1x4_t test_vld1_s64_x4(int64_t con<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD1XN:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD1XN]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)<br class="">@@ -14752,10 +14750,10 @@ void test_vst1q_s64_x2(int64_t *a, int64<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i16* [[TMP9]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x2.v8f16.p0f16(<8 x half> [[TMP7]], <8 x half> [[TMP8]], half* [[TMP9]])<br class=""> // CHECK: ret void<br class=""> void test_vst1q_f16_x2(float16_t *a, float16x8x2_t b) {<br class=""> vst1q_f16_x2(a, b);<br class="">@@ -15098,10 +15096,10 @@ void test_vst1_s64_x2(int64_t *a, int64x<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i16* [[TMP9]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP9:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x2.v4f16.p0f16(<4 x half> [[TMP7]], <4 x half> [[TMP8]], half* [[TMP9]])<br class=""> // CHECK: ret void<br class=""> void test_vst1_f16_x2(float16_t *a, float16x4x2_t b) {<br class=""> vst1_f16_x2(a, b);<br class="">@@ -15484,11 +15482,11 @@ void test_vst1q_s64_x3(int64_t *a, int64<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i16* [[TMP12]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x3.v8f16.p0f16(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], half* [[TMP12]])<br class=""> // CHECK: ret void<br class=""> void test_vst1q_f16_x3(float16_t *a, float16x8x3_t b) {<br class=""> vst1q_f16_x3(a, b);<br class="">@@ -15894,11 +15892,11 @@ void test_vst1_s64_x3(int64_t *a, int64x<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i16* [[TMP12]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x3.v4f16.p0f16(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], half* [[TMP12]])<br class=""> // CHECK: ret void<br class=""> void test_vst1_f16_x3(float16_t *a, float16x4x3_t b) {<br class=""> vst1_f16_x3(a, b);<br class="">@@ -16344,12 +16342,12 @@ void test_vst1q_s64_x4(int64_t *a, int64<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16><br class="">-// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i16* [[TMP15]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half><br class="">+// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x4.v8f16.p0f16(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], half* [[TMP15]])<br class=""> // CHECK: ret void<br class=""> void test_vst1q_f16_x4(float16_t *a, float16x8x4_t b) {<br class=""> vst1q_f16_x4(a, b);<br class="">@@ -16818,12 +16816,12 @@ void test_vst1_s64_x4(int64_t *a, int64x<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16><br class="">-// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to i16*<br class="">-// CHECK: call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i16* [[TMP15]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half><br class="">+// CHECK: [[TMP15:%.*]] = bitcast i8* [[TMP2]] to half*<br class="">+// CHECK: call void @llvm.aarch64.neon.st1x4.v4f16.p0f16(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], half* [[TMP15]])<br class=""> // CHECK: ret void<br class=""> void test_vst1_f16_x4(float16_t *a, float16x4x4_t b) {<br class=""> vst1_f16_x4(a, b);<br class=""><br class="">Modified: cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c (original)<br class="">+++ cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c Thu Jun 1 18:22:29 2017<br class="">@@ -90,12 +90,11 @@ int64x2_t test_vld1q_dup_s64(int64_t *a<br class=""><br class=""> // CHECK-LABEL: define <8 x half> @test_vld1q_dup_f16(half* %a) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]]<br class="">-// CHECK: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0<br class="">-// CHECK: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP3]], <8 x i32> zeroinitializer<br class="">-// CHECK: [[TMP4:%.*]] = bitcast <8 x i16> [[LANE]] to <8 x half><br class="">-// CHECK: ret <8 x half> [[TMP4]]<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]]<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> undef, half [[TMP2]], i32 0<br class="">+// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP3]], <8 x half> [[TMP3]], <8 x i32> zeroinitializer<br class="">+// CHECK: ret <8 x half> [[LANE]]<br class=""> float16x8_t test_vld1q_dup_f16(float16_t *a) {<br class=""> return vld1q_dup_f16(a);<br class=""> }<br class="">@@ -239,12 +238,11 @@ int64x1_t test_vld1_dup_s64(int64_t *a)<br class=""><br class=""> // CHECK-LABEL: define <4 x half> @test_vld1_dup_f16(half* %a) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: [[TMP2:%.*]] = load i16, i16* [[TMP1]]<br class="">-// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[TMP2]], i32 0<br class="">-// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[TMP3]], <4 x i32> zeroinitializer<br class="">-// CHECK: [[TMP4:%.*]] = bitcast <4 x i16> [[LANE]] to <4 x half><br class="">-// CHECK: ret <4 x half> [[TMP4]]<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: [[TMP2:%.*]] = load half, half* [[TMP1]]<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> undef, half [[TMP2]], i32 0<br class="">+// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> zeroinitializer<br class="">+// CHECK: ret <4 x half> [[LANE]]<br class=""> float16x4_t test_vld1_dup_f16(float16_t *a) {<br class=""> return vld1_dup_f16(a);<br class=""> }<br class="">@@ -447,10 +445,10 @@ int64x2x2_t test_vld2q_dup_s64(int64_t<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD2:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2]], { <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD2:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half> } [[VLD2]], { <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 16, i1 false)<br class="">@@ -693,10 +691,10 @@ int64x1x2_t test_vld2_dup_s64(int64_t *<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD2:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2]], { <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD2:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half> } [[VLD2]], { <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 16, i32 8, i1 false)<br class="">@@ -947,10 +945,10 @@ int64x2x3_t test_vld3q_dup_s64(int64_t<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD3:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD3:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 48, i32 16, i1 false)<br class="">@@ -1207,10 +1205,10 @@ int64x1x3_t test_vld3_dup_s64(int64_t *<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD3:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD3:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 24, i32 8, i1 false)<br class="">@@ -1459,10 +1457,10 @@ int64x2x4_t test_vld4q_dup_s64(int64_t<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 16<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD4:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD4:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 64, i32 16, i1 false)<br class="">@@ -1705,10 +1703,10 @@ int64x1x4_t test_vld4_dup_s64(int64_t *<br class=""> // CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8<br class=""> // CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast half* %a to i8*<br class="">-// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i16*<br class="">-// CHECK: [[VLD4:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* [[TMP2]])<br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP3]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to half*<br class="">+// CHECK: [[VLD4:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0f16(half* [[TMP2]])<br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP3]]<br class=""> // CHECK: [[TMP4:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP4]], i8* [[TMP5]], i64 32, i32 8, i1 false)<br class="">@@ -1897,12 +1895,11 @@ int64x2_t test_vld1q_lane_s64(int64_t *<br class=""> // CHECK-LABEL: define <8 x half> @test_vld1q_lane_f16(half* %a, <8 x half> %b) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16><br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]]<br class="">-// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[TMP4]], i32 7<br class="">-// CHECK: [[TMP5:%.*]] = bitcast <8 x i16> [[VLD1_LANE]] to <8 x half><br class="">-// CHECK: ret <8 x half> [[TMP5]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]]<br class="">+// CHECK: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP4]], i32 7<br class="">+// CHECK: ret <8 x half> [[VLD1_LANE]]<br class=""> float16x8_t test_vld1q_lane_f16(float16_t *a, float16x8_t b) {<br class=""> return vld1q_lane_f16(a, b, 7);<br class=""> }<br class="">@@ -2054,12 +2051,11 @@ int64x1_t test_vld1_lane_s64(int64_t *a<br class=""> // CHECK-LABEL: define <4 x half> @test_vld1_lane_f16(half* %a, <4 x half> %b) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16><br class="">-// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: [[TMP4:%.*]] = load i16, i16* [[TMP3]]<br class="">-// CHECK: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[TMP4]], i32 3<br class="">-// CHECK: [[TMP5:%.*]] = bitcast <4 x i16> [[VLD1_LANE]] to <4 x half><br class="">-// CHECK: ret <4 x half> [[TMP5]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP3:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: [[TMP4:%.*]] = load half, half* [[TMP3]]<br class="">+// CHECK: [[VLD1_LANE:%.*]] = insertelement <4 x half> [[TMP2]], half [[TMP4]], i32 3<br class="">+// CHECK: ret <4 x half> [[VLD1_LANE]]<br class=""> float16x4_t test_vld1_lane_f16(float16_t *a, float16x4_t b) {<br class=""> return vld1_lane_f16(a, b, 3);<br class=""> }<br class="">@@ -2495,11 +2491,11 @@ int64x2x2_t test_vld2q_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP6:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16<br class=""> // CHECK: [[TMP7:%.*]] = bitcast <8 x half> [[TMP6]] to <16 x i8><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16><br class="">-// CHECK: [[VLD2_LANE:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i8(<8 x i16> [[TMP8]], <8 x i16> [[TMP9]], i64 7, i8* [[TMP3]])<br class="">-// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16> } [[VLD2_LANE]], { <8 x i16>, <8 x i16> }* [[TMP10]]<br class="">+// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half><br class="">+// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half><br class="">+// CHECK: [[VLD2_LANE:%.*]] = call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0i8(<8 x half> [[TMP8]], <8 x half> [[TMP9]], i64 7, i8* [[TMP3]])<br class="">+// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half> } [[VLD2_LANE]], { <8 x half>, <8 x half> }* [[TMP10]]<br class=""> // CHECK: [[TMP11:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP12:%.*]] = bitcast %struct.float16x8x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP11]], i8* [[TMP12]], i64 32, i32 16, i1 false)<br class="">@@ -2927,11 +2923,11 @@ int64x1x2_t test_vld2_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP6:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8<br class=""> // CHECK: [[TMP7:%.*]] = bitcast <4 x half> [[TMP6]] to <8 x i8><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16><br class="">-// CHECK: [[VLD2_LANE:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i8(<4 x i16> [[TMP8]], <4 x i16> [[TMP9]], i64 3, i8* [[TMP3]])<br class="">-// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16> } [[VLD2_LANE]], { <4 x i16>, <4 x i16> }* [[TMP10]]<br class="">+// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half><br class="">+// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half><br class="">+// CHECK: [[VLD2_LANE:%.*]] = call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0i8(<4 x half> [[TMP8]], <4 x half> [[TMP9]], i64 3, i8* [[TMP3]])<br class="">+// CHECK: [[TMP10:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half> } [[VLD2_LANE]], { <4 x half>, <4 x half> }* [[TMP10]]<br class=""> // CHECK: [[TMP11:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP12:%.*]] = bitcast %struct.float16x4x2_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP11]], i8* [[TMP12]], i64 16, i32 8, i1 false)<br class="">@@ -3364,12 +3360,12 @@ int64x2x3_t test_vld3q_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP8:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16<br class=""> // CHECK: [[TMP9:%.*]] = bitcast <8 x half> [[TMP8]] to <16 x i8><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x i16><br class="">-// CHECK: [[VLD3_LANE:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i8(<8 x i16> [[TMP10]], <8 x i16> [[TMP11]], <8 x i16> [[TMP12]], i64 7, i8* [[TMP3]])<br class="">-// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD3_LANE]], { <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP13]]<br class="">+// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x half><br class="">+// CHECK: [[VLD3_LANE:%.*]] = call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0i8(<8 x half> [[TMP10]], <8 x half> [[TMP11]], <8 x half> [[TMP12]], i64 7, i8* [[TMP3]])<br class="">+// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half> } [[VLD3_LANE]], { <8 x half>, <8 x half>, <8 x half> }* [[TMP13]]<br class=""> // CHECK: [[TMP14:%.*]] = bitcast %struct.float16x8x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP15:%.*]] = bitcast %struct.float16x8x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP14]], i8* [[TMP15]], i64 48, i32 16, i1 false)<br class="">@@ -3889,12 +3885,12 @@ int64x1x3_t test_vld3_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP8:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8<br class=""> // CHECK: [[TMP9:%.*]] = bitcast <4 x half> [[TMP8]] to <8 x i8><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x i16><br class="">-// CHECK: [[VLD3_LANE:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i8(<4 x i16> [[TMP10]], <4 x i16> [[TMP11]], <4 x i16> [[TMP12]], i64 3, i8* [[TMP3]])<br class="">-// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD3_LANE]], { <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP13]]<br class="">+// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x half><br class="">+// CHECK: [[VLD3_LANE:%.*]] = call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0i8(<4 x half> [[TMP10]], <4 x half> [[TMP11]], <4 x half> [[TMP12]], i64 3, i8* [[TMP3]])<br class="">+// CHECK: [[TMP13:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half> } [[VLD3_LANE]], { <4 x half>, <4 x half>, <4 x half> }* [[TMP13]]<br class=""> // CHECK: [[TMP14:%.*]] = bitcast %struct.float16x4x3_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP15:%.*]] = bitcast %struct.float16x4x3_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP14]], i8* [[TMP15]], i64 24, i32 8, i1 false)<br class="">@@ -4454,13 +4450,13 @@ int64x2x4_t test_vld4q_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP10:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16<br class=""> // CHECK: [[TMP11:%.*]] = bitcast <8 x half> [[TMP10]] to <16 x i8><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x i16><br class="">-// CHECK: [[TMP15:%.*]] = bitcast <16 x i8> [[TMP11]] to <8 x i16><br class="">-// CHECK: [[VLD4_LANE:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i8(<8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], <8 x i16> [[TMP15]], i64 7, i8* [[TMP3]])<br class="">-// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }*<br class="">-// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD4_LANE]], { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }* [[TMP16]]<br class="">+// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP5]] to <8 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP7]] to <8 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP9]] to <8 x half><br class="">+// CHECK: [[TMP15:%.*]] = bitcast <16 x i8> [[TMP11]] to <8 x half><br class="">+// CHECK: [[VLD4_LANE:%.*]] = call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0i8(<8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], <8 x half> [[TMP15]], i64 7, i8* [[TMP3]])<br class="">+// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <8 x half>, <8 x half>, <8 x half>, <8 x half> }*<br class="">+// CHECK: store { <8 x half>, <8 x half>, <8 x half>, <8 x half> } [[VLD4_LANE]], { <8 x half>, <8 x half>, <8 x half>, <8 x half> }* [[TMP16]]<br class=""> // CHECK: [[TMP17:%.*]] = bitcast %struct.float16x8x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP18:%.*]] = bitcast %struct.float16x8x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP17]], i8* [[TMP18]], i64 64, i32 16, i1 false)<br class="">@@ -5043,13 +5039,13 @@ int64x1x4_t test_vld4_lane_s64(int64_t<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP10:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8<br class=""> // CHECK: [[TMP11:%.*]] = bitcast <4 x half> [[TMP10]] to <8 x i8><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x i16><br class="">-// CHECK: [[TMP15:%.*]] = bitcast <8 x i8> [[TMP11]] to <4 x i16><br class="">-// CHECK: [[VLD4_LANE:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i8(<4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], <4 x i16> [[TMP15]], i64 3, i8* [[TMP3]])<br class="">-// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }*<br class="">-// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD4_LANE]], { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }* [[TMP16]]<br class="">+// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP5]] to <4 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP7]] to <4 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP9]] to <4 x half><br class="">+// CHECK: [[TMP15:%.*]] = bitcast <8 x i8> [[TMP11]] to <4 x half><br class="">+// CHECK: [[VLD4_LANE:%.*]] = call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0i8(<4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], <4 x half> [[TMP15]], i64 3, i8* [[TMP3]])<br class="">+// CHECK: [[TMP16:%.*]] = bitcast i8* [[TMP2]] to { <4 x half>, <4 x half>, <4 x half>, <4 x half> }*<br class="">+// CHECK: store { <4 x half>, <4 x half>, <4 x half>, <4 x half> } [[VLD4_LANE]], { <4 x half>, <4 x half>, <4 x half>, <4 x half> }* [[TMP16]]<br class=""> // CHECK: [[TMP17:%.*]] = bitcast %struct.float16x4x4_t* [[RETVAL]] to i8*<br class=""> // CHECK: [[TMP18:%.*]] = bitcast %struct.float16x4x4_t* [[__RET]] to i8*<br class=""> // CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP17]], i8* [[TMP18]], i64 32, i32 8, i1 false)<br class="">@@ -5361,10 +5357,10 @@ void test_vst1q_lane_s64(int64_t *a, in<br class=""> // CHECK-LABEL: define void @test_vst1q_lane_f16(half* %a, <8 x half> %b) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16><br class="">-// CHECK: [[TMP3:%.*]] = extractelement <8 x i16> [[TMP2]], i32 7<br class="">-// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: store i16 [[TMP3]], i16* [[TMP4]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP3:%.*]] = extractelement <8 x half> [[TMP2]], i32 7<br class="">+// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: store half [[TMP3]], half* [[TMP4]]<br class=""> // CHECK: ret void<br class=""> void test_vst1q_lane_f16(float16_t *a, float16x8_t b) {<br class=""> vst1q_lane_f16(a, b, 7);<br class="">@@ -5517,10 +5513,10 @@ void test_vst1_lane_s64(int64_t *a, int<br class=""> // CHECK-LABEL: define void @test_vst1_lane_f16(half* %a, <4 x half> %b) #0 {<br class=""> // CHECK: [[TMP0:%.*]] = bitcast half* %a to i8*<br class=""> // CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">-// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16><br class="">-// CHECK: [[TMP3:%.*]] = extractelement <4 x i16> [[TMP2]], i32 3<br class="">-// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to i16*<br class="">-// CHECK: store i16 [[TMP3]], i16* [[TMP4]]<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP3:%.*]] = extractelement <4 x half> [[TMP2]], i32 3<br class="">+// CHECK: [[TMP4:%.*]] = bitcast i8* [[TMP0]] to half*<br class="">+// CHECK: store half [[TMP3]], half* [[TMP4]]<br class=""> // CHECK: ret void<br class=""> void test_vst1_lane_f16(float16_t *a, float16x4_t b) {<br class=""> vst1_lane_f16(a, b, 3);<br class="">@@ -5789,9 +5785,9 @@ void test_vst2q_lane_s64(int64_t *a, in<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <8 x half>], [2 x <8 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX2]], align 16<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <8 x half> [[TMP5]] to <16 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st2lane.v8i16.p0i8(<8 x i16> [[TMP7]], <8 x i16> [[TMP8]], i64 7, i8* [[TMP2]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st2lane.v8f16.p0i8(<8 x half> [[TMP7]], <8 x half> [[TMP8]], i64 7, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst2q_lane_f16(float16_t *a, float16x8x2_t b) {<br class=""> vst2q_lane_f16(a, b, 7);<br class="">@@ -6124,9 +6120,9 @@ void test_vst2_lane_s64(int64_t *a, int<br class=""> // CHECK: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x <4 x half>], [2 x <4 x half>]* [[VAL1]], i64 0, i64 1<br class=""> // CHECK: [[TMP5:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX2]], align 8<br class=""> // CHECK: [[TMP6:%.*]] = bitcast <4 x half> [[TMP5]] to <8 x i8><br class="">-// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st2lane.v4i16.p0i8(<4 x i16> [[TMP7]], <4 x i16> [[TMP8]], i64 3, i8* [[TMP2]])<br class="">+// CHECK: [[TMP7:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP8:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st2lane.v4f16.p0i8(<4 x half> [[TMP7]], <4 x half> [[TMP8]], i64 3, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst2_lane_f16(float16_t *a, float16x4x2_t b) {<br class=""> vst2_lane_f16(a, b, 3);<br class="">@@ -6499,10 +6495,10 @@ void test_vst3q_lane_s64(int64_t *a, in<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <8 x half>], [3 x <8 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX4]], align 16<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <8 x half> [[TMP7]] to <16 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st3lane.v8i16.p0i8(<8 x i16> [[TMP9]], <8 x i16> [[TMP10]], <8 x i16> [[TMP11]], i64 7, i8* [[TMP2]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st3lane.v8f16.p0i8(<8 x half> [[TMP9]], <8 x half> [[TMP10]], <8 x half> [[TMP11]], i64 7, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst3q_lane_f16(float16_t *a, float16x8x3_t b) {<br class=""> vst3q_lane_f16(a, b, 7);<br class="">@@ -6898,10 +6894,10 @@ void test_vst3_lane_s64(int64_t *a, int<br class=""> // CHECK: [[ARRAYIDX4:%.*]] = getelementptr inbounds [3 x <4 x half>], [3 x <4 x half>]* [[VAL3]], i64 0, i64 2<br class=""> // CHECK: [[TMP7:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX4]], align 8<br class=""> // CHECK: [[TMP8:%.*]] = bitcast <4 x half> [[TMP7]] to <8 x i8><br class="">-// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st3lane.v4i16.p0i8(<4 x i16> [[TMP9]], <4 x i16> [[TMP10]], <4 x i16> [[TMP11]], i64 3, i8* [[TMP2]])<br class="">+// CHECK: [[TMP9:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP10:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st3lane.v4f16.p0i8(<4 x half> [[TMP9]], <4 x half> [[TMP10]], <4 x half> [[TMP11]], i64 3, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst3_lane_f16(float16_t *a, float16x4x3_t b) {<br class=""> vst3_lane_f16(a, b, 3);<br class="">@@ -7337,11 +7333,11 @@ void test_vst4q_lane_s64(int64_t *a, in<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <8 x half>], [4 x <8 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <8 x half>, <8 x half>* [[ARRAYIDX6]], align 16<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <8 x half> [[TMP9]] to <16 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st4lane.v8i16.p0i8(<8 x i16> [[TMP11]], <8 x i16> [[TMP12]], <8 x i16> [[TMP13]], <8 x i16> [[TMP14]], i64 7, i8* [[TMP2]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <16 x i8> [[TMP4]] to <8 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP6]] to <8 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP8]] to <8 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <16 x i8> [[TMP10]] to <8 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st4lane.v8f16.p0i8(<8 x half> [[TMP11]], <8 x half> [[TMP12]], <8 x half> [[TMP13]], <8 x half> [[TMP14]], i64 7, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst4q_lane_f16(float16_t *a, float16x8x4_t b) {<br class=""> vst4q_lane_f16(a, b, 7);<br class="">@@ -7800,11 +7796,11 @@ void test_vst4_lane_s64(int64_t *a, int<br class=""> // CHECK: [[ARRAYIDX6:%.*]] = getelementptr inbounds [4 x <4 x half>], [4 x <4 x half>]* [[VAL5]], i64 0, i64 3<br class=""> // CHECK: [[TMP9:%.*]] = load <4 x half>, <4 x half>* [[ARRAYIDX6]], align 8<br class=""> // CHECK: [[TMP10:%.*]] = bitcast <4 x half> [[TMP9]] to <8 x i8><br class="">-// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x i16><br class="">-// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x i16><br class="">-// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x i16><br class="">-// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x i16><br class="">-// CHECK: call void @llvm.aarch64.neon.st4lane.v4i16.p0i8(<4 x i16> [[TMP11]], <4 x i16> [[TMP12]], <4 x i16> [[TMP13]], <4 x i16> [[TMP14]], i64 3, i8* [[TMP2]])<br class="">+// CHECK: [[TMP11:%.*]] = bitcast <8 x i8> [[TMP4]] to <4 x half><br class="">+// CHECK: [[TMP12:%.*]] = bitcast <8 x i8> [[TMP6]] to <4 x half><br class="">+// CHECK: [[TMP13:%.*]] = bitcast <8 x i8> [[TMP8]] to <4 x half><br class="">+// CHECK: [[TMP14:%.*]] = bitcast <8 x i8> [[TMP10]] to <4 x half><br class="">+// CHECK: call void @llvm.aarch64.neon.st4lane.v4f16.p0i8(<4 x half> [[TMP11]], <4 x half> [[TMP12]], <4 x half> [[TMP13]], <4 x half> [[TMP14]], i64 3, i8* [[TMP2]])<br class=""> // CHECK: ret void<br class=""> void test_vst4_lane_f16(float16_t *a, float16x4x4_t b) {<br class=""> vst4_lane_f16(a, b, 3);<br class=""><br class="">Added: cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c?rev=304493&view=auto" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c?rev=304493&view=auto</a><br class="">==============================================================================<br class="">--- cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c (added)<br class="">+++ cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c Thu Jun 1 18:22:29 2017<br class="">@@ -0,0 +1,1633 @@<br class="">+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fp16 -target-feature +v8.2a \<br class="">+// RUN: -fallow-half-arguments-and-returns -S -emit-llvm -o - %s \<br class="">+// RUN: | opt -S -mem2reg \<br class="">+// RUN: | FileCheck %s<br class="">+<br class="">+// REQUIRES: aarch64-registered-target<br class="">+<br class="">+#include <arm_neon.h><br class="">+<br class="">+// CHECK-LABEL: test_vabs_f16<br class="">+// CHECK: [[ABS:%.*]] = call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[ABS]]<br class="">+float16x4_t test_vabs_f16(float16x4_t a) {<br class="">+ return vabs_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vabsq_f16<br class="">+// CHECK: [[ABS:%.*]] = call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[ABS]]<br class="">+float16x8_t test_vabsq_f16(float16x8_t a) {<br class="">+ return vabsq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vceqz_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oeq <4 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vceqz_f16(float16x4_t a) {<br class="">+ return vceqz_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vceqzq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oeq <8 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vceqzq_f16(float16x8_t a) {<br class="">+ return vceqzq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgez_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oge <4 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcgez_f16(float16x4_t a) {<br class="">+ return vcgez_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgezq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oge <8 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcgezq_f16(float16x8_t a) {<br class="">+ return vcgezq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgtz_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ogt <4 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcgtz_f16(float16x4_t a) {<br class="">+ return vcgtz_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgtzq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ogt <8 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcgtzq_f16(float16x8_t a) {<br class="">+ return vcgtzq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vclez_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ole <4 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vclez_f16(float16x4_t a) {<br class="">+ return vclez_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vclezq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ole <8 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vclezq_f16(float16x8_t a) {<br class="">+ return vclezq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcltz_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp olt <4 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcltz_f16(float16x4_t a) {<br class="">+ return vcltz_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcltzq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp olt <8 x half> %a, zeroinitializer<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcltzq_f16(float16x8_t a) {<br class="">+ return vcltzq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_f16_s16<br class="">+// CHECK: [[VCVT:%.*]] = sitofp <4 x i16> %a to <4 x half><br class="">+// CHECK: ret <4 x half> [[VCVT]]<br class="">+float16x4_t test_vcvt_f16_s16 (int16x4_t a) {<br class="">+ return vcvt_f16_s16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_f16_s16<br class="">+// CHECK: [[VCVT:%.*]] = sitofp <8 x i16> %a to <8 x half><br class="">+// CHECK: ret <8 x half> [[VCVT]]<br class="">+float16x8_t test_vcvtq_f16_s16 (int16x8_t a) {<br class="">+ return vcvtq_f16_s16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_f16_u16<br class="">+// CHECK: [[VCVT:%.*]] = uitofp <4 x i16> %a to <4 x half><br class="">+// CHECK: ret <4 x half> [[VCVT]]<br class="">+float16x4_t test_vcvt_f16_u16 (uint16x4_t a) {<br class="">+ return vcvt_f16_u16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_f16_u16<br class="">+// CHECK: [[VCVT:%.*]] = uitofp <8 x i16> %a to <8 x half><br class="">+// CHECK: ret <8 x half> [[VCVT]]<br class="">+float16x8_t test_vcvtq_f16_u16 (uint16x8_t a) {<br class="">+ return vcvtq_f16_u16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = fptosi <4 x half> %a to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvt_s16_f16 (float16x4_t a) {<br class="">+ return vcvt_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = fptosi <8 x half> %a to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtq_s16_f16 (float16x8_t a) {<br class="">+ return vcvtq_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = fptoui <4 x half> %a to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvt_u16_f16 (float16x4_t a) {<br class="">+ return vcvt_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = fptoui <8 x half> %a to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtq_u16_f16 (float16x8_t a) {<br class="">+ return vcvtq_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvta_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtas.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvta_s16_f16 (float16x4_t a) {<br class="">+ return vcvta_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtaq_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtas.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtaq_s16_f16 (float16x8_t a) {<br class="">+ return vcvtaq_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtm_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtms.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvtm_s16_f16 (float16x4_t a) {<br class="">+ return vcvtm_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtmq_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtms.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtmq_s16_f16 (float16x8_t a) {<br class="">+ return vcvtmq_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtm_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtmu.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+uint16x4_t test_vcvtm_u16_f16 (float16x4_t a) {<br class="">+ return vcvtm_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtmq_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtmu.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+uint16x8_t test_vcvtmq_u16_f16 (float16x8_t a) {<br class="">+ return vcvtmq_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtn_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtns.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvtn_s16_f16 (float16x4_t a) {<br class="">+ return vcvtn_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtnq_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtns.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtnq_s16_f16 (float16x8_t a) {<br class="">+ return vcvtnq_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtn_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtnu.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+uint16x4_t test_vcvtn_u16_f16 (float16x4_t a) {<br class="">+ return vcvtn_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtnq_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtnu.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+uint16x8_t test_vcvtnq_u16_f16 (float16x8_t a) {<br class="">+ return vcvtnq_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtp_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtps.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+int16x4_t test_vcvtp_s16_f16 (float16x4_t a) {<br class="">+ return vcvtp_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtpq_s16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtps.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+int16x8_t test_vcvtpq_s16_f16 (float16x8_t a) {<br class="">+ return vcvtpq_s16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtp_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.fcvtpu.v4i16.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[VCVT]]<br class="">+uint16x4_t test_vcvtp_u16_f16 (float16x4_t a) {<br class="">+ return vcvtp_u16_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtpq_u16_f16<br class="">+// CHECK: [[VCVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.fcvtpu.v8i16.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[VCVT]]<br class="">+uint16x8_t test_vcvtpq_u16_f16 (float16x8_t a) {<br class="">+ return vcvtpq_u16_f16(a);<br class="">+}<br class="">+<br class="">+// FIXME: Fix the zero constant when fp16 non-storage-only type becomes available.<br class="">+// CHECK-LABEL: test_vneg_f16<br class="">+// CHECK: [[NEG:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a<br class="">+// CHECK: ret <4 x half> [[NEG]]<br class="">+float16x4_t test_vneg_f16(float16x4_t a) {<br class="">+ return vneg_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vnegq_f16<br class="">+// CHECK: [[NEG:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a<br class="">+// CHECK: ret <8 x half> [[NEG]]<br class="">+float16x8_t test_vnegq_f16(float16x8_t a) {<br class="">+ return vnegq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrecpe_f16<br class="">+// CHECK: [[RCP:%.*]] = call <4 x half> @llvm.aarch64.neon.frecpe.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RCP]]<br class="">+float16x4_t test_vrecpe_f16(float16x4_t a) {<br class="">+ return vrecpe_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrecpeq_f16<br class="">+// CHECK: [[RCP:%.*]] = call <8 x half> @llvm.aarch64.neon.frecpe.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RCP]]<br class="">+float16x8_t test_vrecpeq_f16(float16x8_t a) {<br class="">+ return vrecpeq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrnd_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.trunc.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrnd_f16(float16x4_t a) {<br class="">+ return vrnd_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndq_f16(float16x8_t a) {<br class="">+ return vrndq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrnda_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.round.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrnda_f16(float16x4_t a) {<br class="">+ return vrnda_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndaq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.round.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndaq_f16(float16x8_t a) {<br class="">+ return vrndaq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndi_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrndi_f16(float16x4_t a) {<br class="">+ return vrndi_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndiq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndiq_f16(float16x8_t a) {<br class="">+ return vrndiq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndm_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.floor.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrndm_f16(float16x4_t a) {<br class="">+ return vrndm_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndmq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndmq_f16(float16x8_t a) {<br class="">+ return vrndmq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndn_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.aarch64.neon.frintn.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrndn_f16(float16x4_t a) {<br class="">+ return vrndn_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndnq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.aarch64.neon.frintn.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndnq_f16(float16x8_t a) {<br class="">+ return vrndnq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndp_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.ceil.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrndp_f16(float16x4_t a) {<br class="">+ return vrndp_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndpq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndpq_f16(float16x8_t a) {<br class="">+ return vrndpq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndx_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.rint.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrndx_f16(float16x4_t a) {<br class="">+ return vrndx_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrndxq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.rint.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrndxq_f16(float16x8_t a) {<br class="">+ return vrndxq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrsqrte_f16<br class="">+// CHECK: [[RND:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrte.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[RND]]<br class="">+float16x4_t test_vrsqrte_f16(float16x4_t a) {<br class="">+ return vrsqrte_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrsqrteq_f16<br class="">+// CHECK: [[RND:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrte.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[RND]]<br class="">+float16x8_t test_vrsqrteq_f16(float16x8_t a) {<br class="">+ return vrsqrteq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vsqrt_f16<br class="">+// CHECK: [[SQR:%.*]] = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[SQR]]<br class="">+float16x4_t test_vsqrt_f16(float16x4_t a) {<br class="">+ return vsqrt_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vsqrtq_f16<br class="">+// CHECK: [[SQR:%.*]] = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[SQR]]<br class="">+float16x8_t test_vsqrtq_f16(float16x8_t a) {<br class="">+ return vsqrtq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vadd_f16<br class="">+// CHECK: [[ADD:%.*]] = fadd <4 x half> %a, %b<br class="">+// CHECK: ret <4 x half> [[ADD]]<br class="">+float16x4_t test_vadd_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vadd_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vaddq_f16<br class="">+// CHECK: [[ADD:%.*]] = fadd <8 x half> %a, %b<br class="">+// CHECK: ret <8 x half> [[ADD]]<br class="">+float16x8_t test_vaddq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vaddq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vabd_f16<br class="">+// CHECK: [[ABD:%.*]] = call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[ABD]]<br class="">+float16x4_t test_vabd_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vabd_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vabdq_f16<br class="">+// CHECK: [[ABD:%.*]] = call <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[ABD]]<br class="">+float16x8_t test_vabdq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vabdq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcage_f16<br class="">+// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x i16> [[ABS]]<br class="">+uint16x4_t test_vcage_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcage_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcageq_f16<br class="">+// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x i16> [[ABS]]<br class="">+uint16x8_t test_vcageq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcageq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcagt_f16<br class="">+// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x i16> [[ABS]]<br class="">+uint16x4_t test_vcagt_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcagt_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcagtq_f16<br class="">+// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x i16> [[ABS]]<br class="">+uint16x8_t test_vcagtq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcagtq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcale_f16<br class="">+// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[ABS]]<br class="">+uint16x4_t test_vcale_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcale_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcaleq_f16<br class="">+// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[ABS]]<br class="">+uint16x8_t test_vcaleq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcaleq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcalt_f16<br class="">+// CHECK: [[ABS:%.*]] = call <4 x i16> @llvm.aarch64.neon.facgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a)<br class="">+// CHECK: ret <4 x i16> [[ABS]]<br class="">+uint16x4_t test_vcalt_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcalt_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcaltq_f16<br class="">+// CHECK: [[ABS:%.*]] = call <8 x i16> @llvm.aarch64.neon.facgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a)<br class="">+// CHECK: ret <8 x i16> [[ABS]]<br class="">+uint16x8_t test_vcaltq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcaltq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vceq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oeq <4 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vceq_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vceq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vceqq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oeq <8 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vceqq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vceqq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcge_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oge <4 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcge_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcge_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgeq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp oge <8 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcgeq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcgeq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgt_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ogt <4 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcgt_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcgt_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcgtq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ogt <8 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcgtq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcgtq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcle_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ole <4 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vcle_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vcle_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcleq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp ole <8 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcleq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcleq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vclt_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp olt <4 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16><br class="">+// CHECK: ret <4 x i16> [[TMP2]]<br class="">+uint16x4_t test_vclt_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vclt_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcltq_f16<br class="">+// CHECK: [[TMP1:%.*]] = fcmp olt <8 x half> %a, %b<br class="">+// CHECK: [[TMP2:%.*]] = sext <8 x i1> [[TMP1:%.*]] to <8 x i16><br class="">+// CHECK: ret <8 x i16> [[TMP2]]<br class="">+uint16x8_t test_vcltq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vcltq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_n_f16_s16<br class="">+// CHECK: [[CVT:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16> %vcvt_n, i32 2)<br class="">+// CHECK: ret <4 x half> [[CVT]]<br class="">+float16x4_t test_vcvt_n_f16_s16(int16x4_t a) {<br class="">+ return vcvt_n_f16_s16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_n_f16_s16<br class="">+// CHECK: [[CVT:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16> %vcvt_n, i32 2)<br class="">+// CHECK: ret <8 x half> [[CVT]]<br class="">+float16x8_t test_vcvtq_n_f16_s16(int16x8_t a) {<br class="">+ return vcvtq_n_f16_s16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_n_f16_u16<br class="">+// CHECK: [[CVT:%.*]] = call <4 x half> @llvm.aarch64.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16> %vcvt_n, i32 2)<br class="">+// CHECK: ret <4 x half> [[CVT]]<br class="">+float16x4_t test_vcvt_n_f16_u16(uint16x4_t a) {<br class="">+ return vcvt_n_f16_u16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_n_f16_u16<br class="">+// CHECK: [[CVT:%.*]] = call <8 x half> @llvm.aarch64.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16> %vcvt_n, i32 2)<br class="">+// CHECK: ret <8 x half> [[CVT]]<br class="">+float16x8_t test_vcvtq_n_f16_u16(uint16x8_t a) {<br class="">+ return vcvtq_n_f16_u16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_n_s16_f16<br class="">+// CHECK: [[CVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half> %vcvt_n, i32 2)<br class="">+// CHECK: ret <4 x i16> [[CVT]]<br class="">+int16x4_t test_vcvt_n_s16_f16(float16x4_t a) {<br class="">+ return vcvt_n_s16_f16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_n_s16_f16<br class="">+// CHECK: [[CVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half> %vcvt_n, i32 2)<br class="">+// CHECK: ret <8 x i16> [[CVT]]<br class="">+int16x8_t test_vcvtq_n_s16_f16(float16x8_t a) {<br class="">+ return vcvtq_n_s16_f16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvt_n_u16_f16<br class="">+// CHECK: [[CVT:%.*]] = call <4 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half> %vcvt_n, i32 2)<br class="">+// CHECK: ret <4 x i16> [[CVT]]<br class="">+uint16x4_t test_vcvt_n_u16_f16(float16x4_t a) {<br class="">+ return vcvt_n_u16_f16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vcvtq_n_u16_f16<br class="">+// CHECK: [[CVT:%.*]] = call <8 x i16> @llvm.aarch64.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half> %vcvt_n, i32 2)<br class="">+// CHECK: ret <8 x i16> [[CVT]]<br class="">+uint16x8_t test_vcvtq_n_u16_f16(float16x8_t a) {<br class="">+ return vcvtq_n_u16_f16(a, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdiv_f16<br class="">+// CHECK: [[DIV:%.*]] = fdiv <4 x half> %a, %b<br class="">+// CHECK: ret <4 x half> [[DIV]]<br class="">+float16x4_t test_vdiv_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vdiv_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdivq_f16<br class="">+// CHECK: [[DIV:%.*]] = fdiv <8 x half> %a, %b<br class="">+// CHECK: ret <8 x half> [[DIV]]<br class="">+float16x8_t test_vdivq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vdivq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmax_f16<br class="">+// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmax.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MAX]]<br class="">+float16x4_t test_vmax_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmax_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxq_f16<br class="">+// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmax.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MAX]]<br class="">+float16x8_t test_vmaxq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmaxq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxnm_f16<br class="">+// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MAX]]<br class="">+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmaxnm_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxnmq_f16<br class="">+// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnm.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MAX]]<br class="">+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmaxnmq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmin_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fmin.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vmin_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmin_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fmin.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vminq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vminq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminnm_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vminnm_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminnmq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnm.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vminnmq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmul_f16<br class="">+// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, %b<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmul_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmul_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulq_f16<br class="">+// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, %b<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmulq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulx_f16<br class="">+// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmulx_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmulx_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulxq_f16<br class="">+// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulxq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmulxq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpadd_f16<br class="">+// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.aarch64.neon.addp.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[ADD]]<br class="">+float16x4_t test_vpadd_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vpadd_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpaddq_f16<br class="">+// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.aarch64.neon.addp.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[ADD]]<br class="">+float16x8_t test_vpaddq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vpaddq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpmax_f16<br class="">+// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxp.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MAX]]<br class="">+float16x4_t test_vpmax_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vpmax_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpmaxq_f16<br class="">+// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxp.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MAX]]<br class="">+float16x8_t test_vpmaxq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vpmaxq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpmaxnm_f16<br class="">+// CHECK: [[MAX:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MAX]]<br class="">+float16x4_t test_vpmaxnm_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vpmaxnm_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpmaxnmq_f16<br class="">+// CHECK: [[MAX:%.*]] = call <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MAX]]<br class="">+float16x8_t test_vpmaxnmq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vpmaxnmq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpmin_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminp.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vpmin_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vpmin_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpminq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminp.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vpminq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vpminq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpminnm_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vpminnm_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vpminnm_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vpminnmq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vpminnmq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vpminnmq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrecps_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.frecps.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vrecps_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vrecps_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrecpsq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.frecps.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vrecpsq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vrecpsq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrsqrts_f16<br class="">+// CHECK: [[MIN:%.*]] = call <4 x half> @llvm.aarch64.neon.frsqrts.v4f16(<4 x half> %a, <4 x half> %b)<br class="">+// CHECK: ret <4 x half> [[MIN]]<br class="">+float16x4_t test_vrsqrts_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vrsqrts_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vrsqrtsq_f16<br class="">+// CHECK: [[MIN:%.*]] = call <8 x half> @llvm.aarch64.neon.frsqrts.v8f16(<8 x half> %a, <8 x half> %b)<br class="">+// CHECK: ret <8 x half> [[MIN]]<br class="">+float16x8_t test_vrsqrtsq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vrsqrtsq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vsub_f16<br class="">+// CHECK: [[ADD:%.*]] = fsub <4 x half> %a, %b <br class="">+// CHECK: ret <4 x half> [[ADD]]<br class="">+float16x4_t test_vsub_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vsub_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vsubq_f16<br class="">+// CHECK: [[ADD:%.*]] = fsub <8 x half> %a, %b<br class="">+// CHECK: ret <8 x half> [[ADD]]<br class="">+float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vsubq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfma_f16<br class="">+// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[ADD]]<br class="">+float16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) {<br class="">+ return vfma_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmaq_f16<br class="">+// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[ADD]]<br class="">+float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {<br class="">+ return vfmaq_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfms_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[ADD]]<br class="">+float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {<br class="">+ return vfms_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsq_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[ADD]]<br class="">+float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {<br class="">+ return vfmsq_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfma_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])<br class="">+// CHECK: ret <4 x half> [[FMLA]]<br class="">+float16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {<br class="">+ return vfma_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmaq_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])<br class="">+// CHECK: ret <8 x half> [[FMLA]]<br class="">+float16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {<br class="">+ return vfmaq_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfma_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])<br class="">+// CHECK: ret <4 x half> [[FMLA]]<br class="">+float16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {<br class="">+ return vfma_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmaq_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])<br class="">+// CHECK: ret <8 x half> [[FMLA]]<br class="">+float16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {<br class="">+ return vfmaq_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfma_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3<br class="">+// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> [[TMP3]], <4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[FMA]]<br class="">+float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) {<br class="">+ return vfma_n_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmaq_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7<br class="">+// CHECK: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> [[TMP7]], <8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[FMA]]<br class="">+float16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {<br class="">+ return vfmaq_n_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmah_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[EXTR:%.*]] = extractelement <4 x half> [[TMP1]], i32 3<br class="">+// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)<br class="">+// CHECK: ret half [[FMA]]<br class="">+float16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) {<br class="">+ return vfmah_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmah_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[EXTR:%.*]] = extractelement <8 x half> [[TMP1]], i32 7<br class="">+// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)<br class="">+// CHECK: ret half [[FMA]]<br class="">+float16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) {<br class="">+ return vfmah_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfms_lane_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> <i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])<br class="">+// CHECK: ret <4 x half> [[FMA]]<br class="">+float16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {<br class="">+ return vfms_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsq_lane_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])<br class="">+// CHECK: ret <8 x half> [[FMLA]]<br class="">+float16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {<br class="">+ return vfmsq_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfms_laneq_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> <i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])<br class="">+// CHECK: ret <4 x half> [[FMLA]]<br class="">+float16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {<br class="">+ return vfms_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsq_laneq_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half><br class="">+// CHECK: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])<br class="">+// CHECK: ret <8 x half> [[FMLA]]<br class="">+float16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {<br class="">+ return vfmsq_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfms_n_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3<br class="">+// CHECK: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> [[TMP3]], <4 x half> %a)<br class="">+// CHECK: ret <4 x half> [[FMA]]<br class="">+float16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) {<br class="">+ return vfms_n_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsq_n_f16<br class="">+// CHECK: [[SUB:%.*]] = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7<br class="">+// CHECK: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> [[TMP7]], <8 x half> %a)<br class="">+// CHECK: ret <8 x half> [[FMA]]<br class="">+float16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {<br class="">+ return vfmsq_n_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsh_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = fpext half %b to float<br class="">+// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]]<br class="">+// CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half><br class="">+// CHECK: [[EXTR:%.*]] = extractelement <4 x half> [[TMP3]], i32 3<br class="">+// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)<br class="">+// CHECK: ret half [[FMA]]<br class="">+float16_t test_vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t c) {<br class="">+ return vfmsh_lane_f16(a, b, c, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vfmsh_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = fpext half %b to float<br class="">+// CHECK: [[TMP1:%.*]] = fsub float -0.000000e+00, [[TMP0]]<br class="">+// CHECK: [[SUB:%.*]] = fptrunc float [[TMP1]] to half<br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half><br class="">+// CHECK: [[EXTR:%.*]] = extractelement <8 x half> [[TMP3]], i32 7<br class="">+// CHECK: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)<br class="">+// CHECK: ret half [[FMA]]<br class="">+float16_t test_vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t c) {<br class="">+ return vfmsh_laneq_f16(a, b, c, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmul_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP0]]<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmul_lane_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmul_lane_f16(a, b, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulq_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP0]]<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulq_lane_f16(float16x8_t a, float16x4_t b) {<br class="">+ return vmulq_lane_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmul_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <4 x i32> <i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP0]]<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmul_laneq_f16(float16x4_t a, float16x8_t b) {<br class="">+ return vmul_laneq_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulq_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP0]]<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulq_laneq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmulq_laneq_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmul_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %b, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %b, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %b, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %b, i32 3<br class="">+// CHECK: [[MUL:%.*]] = fmul <4 x half> %a, [[TMP3]]<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmul_n_f16(float16x4_t a, float16_t b) {<br class="">+ return vmul_n_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulq_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %b, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %b, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %b, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %b, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %b, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %b, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %b, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %b, i32 7<br class="">+// CHECK: [[MUL:%.*]] = fmul <8 x half> %a, [[TMP7]]<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulq_n_f16(float16x8_t a, float16_t b) {<br class="">+ return vmulq_n_f16(a, b);<br class="">+}<br class="">+<br class="">+// FIXME: Fix it when fp16 non-storage-only type becomes available.<br class="">+// CHECK-LABEL: test_vmulh_lane_f16<br class="">+// CHECK: [[CONV0:%.*]] = fpext half %a to float<br class="">+// CHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float<br class="">+// CHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]<br class="">+// CHECK: [[CONV3:%.*]] = fptrunc float %mul to half<br class="">+// CHECK: ret half [[CONV3:%.*]]<br class="">+float16_t test_vmulh_lane_f16(float16_t a, float16x4_t b) {<br class="">+ return vmulh_lane_f16(a, b, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulh_laneq_f16<br class="">+// CHECK: [[CONV0:%.*]] = fpext half %a to float<br class="">+// CHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float<br class="">+// CHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]<br class="">+// CHECK: [[CONV3:%.*]] = fptrunc float %mul to half<br class="">+// CHECK: ret half [[CONV3:%.*]]<br class="">+float16_t test_vmulh_laneq_f16(float16_t a, float16x8_t b) {<br class="">+ return vmulh_laneq_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulx_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP0]])<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmulx_lane_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vmulx_lane_f16(a, b, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulxq_lane_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <4 x half> %b, <4 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP0]])<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulxq_lane_f16(float16x8_t a, float16x4_t b) {<br class="">+ return vmulxq_lane_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulx_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <4 x i32> <i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP0]])<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmulx_laneq_f16(float16x4_t a, float16x8_t b) {<br class="">+ return vmulx_laneq_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulxq_laneq_f16<br class="">+// CHECK: [[TMP0:%.*]] = shufflevector <8 x half> %b, <8 x half> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP0]])<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulxq_laneq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vmulxq_laneq_f16(a, b, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulx_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %b, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %b, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %b, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %b, i32 3<br class="">+// CHECK: [[MUL:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> [[TMP3]])<br class="">+// CHECK: ret <4 x half> [[MUL]]<br class="">+float16x4_t test_vmulx_n_f16(float16x4_t a, float16_t b) {<br class="">+ return vmulx_n_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmulxq_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %b, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %b, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %b, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %b, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %b, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %b, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %b, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %b, i32 7<br class="">+// CHECK: [[MUL:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> [[TMP7]])<br class="">+// CHECK: ret <8 x half> [[MUL]]<br class="">+float16x8_t test_vmulxq_n_f16(float16x8_t a, float16_t b) {<br class="">+ return vmulxq_n_f16(a, b);<br class="">+}<br class="">+<br class="">+/* TODO: Not implemented yet (needs scalar intrinsic from arm_fp16.h)<br class="">+// CCHECK-LABEL: test_vmulxh_lane_f16<br class="">+// CCHECK: [[CONV0:%.*]] = fpext half %a to float<br class="">+// CCHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float<br class="">+// CCHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]<br class="">+// CCHECK: [[CONV3:%.*]] = fptrunc float %mul to half<br class="">+// CCHECK: ret half [[CONV3:%.*]]<br class="">+float16_t test_vmulxh_lane_f16(float16_t a, float16x4_t b) {<br class="">+ return vmulxh_lane_f16(a, b, 3);<br class="">+}<br class="">+<br class="">+// CCHECK-LABEL: test_vmulxh_laneq_f16<br class="">+// CCHECK: [[CONV0:%.*]] = fpext half %a to float<br class="">+// CCHECK: [[CONV1:%.*]] = fpext half %{{.*}} to float<br class="">+// CCHECK: [[MUL:%.*]] = fmul float [[CONV0:%.*]], [[CONV0:%.*]]<br class="">+// CCHECK: [[CONV3:%.*]] = fptrunc float %mul to half<br class="">+// CCHECK: ret half [[CONV3:%.*]]<br class="">+float16_t test_vmulxh_laneq_f16(float16_t a, float16x8_t b) {<br class="">+ return vmulxh_laneq_f16(a, b, 7);<br class="">+}<br class="">+*/<br class="">+<br class="">+// CHECK-LABEL: test_vmaxv_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vmaxv_f16(float16x4_t a) {<br class="">+ return vmaxv_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxvq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vmaxvq_f16(float16x8_t a) {<br class="">+ return vmaxvq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminv_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vminv_f16(float16x4_t a) {<br class="">+ return vminv_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminvq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v8f16(<8 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vminvq_f16(float16x8_t a) {<br class="">+ return vminvq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxnmv_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v4f16(<4 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vmaxnmv_f16(float16x4_t a) {<br class="">+ return vmaxnmv_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmaxnmvq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v8f16(<8 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vmaxnmvq_f16(float16x8_t a) {<br class="">+ return vmaxnmvq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminnmv_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v4f16(<4 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vminnmv_f16(float16x4_t a) {<br class="">+ return vminnmv_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vminnmvq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[MAX:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v8f16(<8 x half> [[TMP1]])<br class="">+// CHECK: ret half [[MAX]]<br class="">+float16_t test_vminnmvq_f16(float16x8_t a) {<br class="">+ return vminnmvq_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vbsl_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %c to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16><br class="">+// CHECK: [[TMP4:%.*]] = and <4 x i16> %a, [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1><br class="">+// CHECK: [[TMP6:%.*]] = and <4 x i16> [[TMP5]], [[TMP3]]<br class="">+// CHECK: [[TMP7:%.*]] = or <4 x i16> [[TMP4]], [[TMP6]]<br class="">+// CHECK: [[TMP8:%.*]] = bitcast <4 x i16> [[TMP7]] to <4 x half><br class="">+// CHECK: ret <4 x half> [[TMP8]]<br class="">+float16x4_t test_vbsl_f16(uint16x4_t a, float16x4_t b, float16x4_t c) {<br class="">+ return vbsl_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vbslq_f16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %c to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16><br class="">+// CHECK: [[TMP4:%.*]] = and <8 x i16> %a, [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1><br class="">+// CHECK: [[TMP6:%.*]] = and <8 x i16> [[TMP5]], [[TMP3]]<br class="">+// CHECK: [[TMP7:%.*]] = or <8 x i16> [[TMP4]], [[TMP6]]<br class="">+// CHECK: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP7]] to <8 x half><br class="">+// CHECK: ret <8 x half> [[TMP8]]<br class="">+float16x8_t test_vbslq_f16(uint16x8_t a, float16x8_t b, float16x8_t c) {<br class="">+ return vbslq_f16(a, b, c);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vzip_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5><br class="">+// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]<br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7><br class="">+// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)<br class="">+float16x4x2_t test_vzip_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vzip_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vzipq_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11><br class="">+// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]]<br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15><br class="">+// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)<br class="">+float16x8x2_t test_vzipq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vzipq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vuzp_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6><br class="">+// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]<br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7><br class="">+// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)<br class="">+float16x4x2_t test_vuzp_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vuzp_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vuzpq_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14><br class="">+// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]]<br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15><br class="">+// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)<br class="">+float16x8x2_t test_vuzpq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vuzpq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vtrn_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x4x2_t, align 8<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6><br class="">+// CHECK: store <4 x half> [[VZIP0_I]], <4 x half>* [[TMP1]]<br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <4 x half>, <4 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7><br class="">+// CHECK: store <4 x half> [[VZIP1_I]], <4 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x4x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x4x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 16, i32 8, i1 false)<br class="">+float16x4x2_t test_vtrn_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vtrn_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vtrnq_f16<br class="">+// CHECK: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[__RET_I:%.*]] = alloca %struct.float16x8x2_t, align 16<br class="">+// CHECK: [[TMP0:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x half>*<br class="">+// CHECK: [[VZIP0_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14><br class="">+// CHECK: store <8 x half> [[VZIP0_I]], <8 x half>* [[TMP1]] <br class="">+// CHECK: [[TMP2:%.*]] = getelementptr inbounds <8 x half>, <8 x half>* [[TMP1]], i32 1<br class="">+// CHECK: [[VZIP1_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15><br class="">+// CHECK: store <8 x half> [[VZIP1_I]], <8 x half>* [[TMP2]]<br class="">+// CHECK: [[TMP5:%.*]] = bitcast %struct.float16x8x2_t* [[RETVAL]] to i8*<br class="">+// CHECK: [[TMP6:%.*]] = bitcast %struct.float16x8x2_t* [[__RET_I]] to i8*<br class="">+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[TMP5]], i8* [[TMP6]], i64 32, i32 16, i1 false)<br class="">+float16x8x2_t test_vtrnq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vtrnq_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmov_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %a, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %a, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %a, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %a, i32 3<br class="">+// CHECK: ret <4 x half> [[TMP3]]<br class="">+float16x4_t test_vmov_n_f16(float16_t a) {<br class="">+ return vmov_n_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vmovq_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %a, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %a, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %a, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %a, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %a, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %a, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %a, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %a, i32 7<br class="">+// CHECK: ret <8 x half> [[TMP7]]<br class="">+float16x8_t test_vmovq_n_f16(float16_t a) {<br class="">+ return vmovq_n_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdup_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <4 x half> undef, half %a, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %a, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %a, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %a, i32 3<br class="">+// CHECK: ret <4 x half> [[TMP3]]<br class="">+float16x4_t test_vdup_n_f16(float16_t a) {<br class="">+ return vdup_n_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdupq_n_f16<br class="">+// CHECK: [[TMP0:%.*]] = insertelement <8 x half> undef, half %a, i32 0<br class="">+// CHECK: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %a, i32 1<br class="">+// CHECK: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %a, i32 2<br class="">+// CHECK: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %a, i32 3<br class="">+// CHECK: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %a, i32 4<br class="">+// CHECK: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %a, i32 5<br class="">+// CHECK: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %a, i32 6<br class="">+// CHECK: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %a, i32 7<br class="">+// CHECK: ret <8 x half> [[TMP7]]<br class="">+float16x8_t test_vdupq_n_f16(float16_t a) {<br class="">+ return vdupq_n_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdup_lane_f16<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3><br class="">+// CHECK: ret <4 x half> [[SHFL]]<br class="">+float16x4_t test_vdup_lane_f16(float16x4_t a) {<br class="">+ return vdup_lane_f16(a, 3);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: test_vdupq_lane_f16<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7><br class="">+// CHECK: ret <8 x half> [[SHFL]]<br class="">+float16x8_t test_vdupq_lane_f16(float16x4_t a) {<br class="">+ return vdupq_lane_f16(a, 7);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vext_f16(<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half><br class="">+// CHECK: [[VEXT:%.*]] = shufflevector <4 x half> [[TMP2]], <4 x half> [[TMP3]], <4 x i32> <i32 2, i32 3, i32 4, i32 5><br class="">+// CHECK: ret <4 x half> [[VEXT]]<br class="">+float16x4_t test_vext_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vext_f16(a, b, 2);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vextq_f16(<br class="">+// CHECK: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8><br class="">+// CHECK: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8><br class="">+// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half><br class="">+// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half><br class="">+// CHECK: [[VEXT:%.*]] = shufflevector <8 x half> [[TMP2]], <8 x half> [[TMP3]], <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12><br class="">+// CHECK: ret <8 x half> [[VEXT]]<br class="">+float16x8_t test_vextq_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vextq_f16(a, b, 5);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vrev64_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0><br class="">+// CHECK: ret <4 x half> [[SHFL]]<br class="">+float16x4_t test_vrev64_f16(float16x4_t a) {<br class="">+ return vrev64_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vrev64q_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4><br class="">+// CHECK: ret <8 x half> [[SHFL]]<br class="">+float16x8_t test_vrev64q_f16(float16x8_t a) {<br class="">+ return vrev64q_f16(a);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vzip1_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5><br class="">+// CHECK: ret <4 x half> [[SHFL]]<br class="">+float16x4_t test_vzip1_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vzip1_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vzip1q_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11><br class="">+// CHECK: ret <8 x half> [[SHFL]]<br class="">+float16x8_t test_vzip1q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vzip1q_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vzip2_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7><br class="">+// CHECK: ret <4 x half> [[SHFL]]<br class="">+float16x4_t test_vzip2_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vzip2_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vzip2q_f16(<br class="">+// CHECK: [[SHFL:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15><br class="">+// CHECK: ret <8 x half> [[SHFL]]<br class="">+float16x8_t test_vzip2q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vzip2q_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vuzp1_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6><br class="">+// CHECK: ret <4 x half> [[SHUFFLE_I]]<br class="">+float16x4_t test_vuzp1_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vuzp1_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vuzp1q_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14><br class="">+// CHECK: ret <8 x half> [[SHUFFLE_I]]<br class="">+float16x8_t test_vuzp1q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vuzp1q_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vuzp2_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7><br class="">+// CHECK: ret <4 x half> [[SHUFFLE_I]]<br class="">+float16x4_t test_vuzp2_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vuzp2_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vuzp2q_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15><br class="">+// CHECK: ret <8 x half> [[SHUFFLE_I]]<br class="">+float16x8_t test_vuzp2q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vuzp2q_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vtrn1_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6><br class="">+// CHECK: ret <4 x half> [[SHUFFLE_I]]<br class="">+float16x4_t test_vtrn1_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vtrn1_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vtrn1q_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14><br class="">+// CHECK: ret <8 x half> [[SHUFFLE_I]]<br class="">+float16x8_t test_vtrn1q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vtrn1q_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vtrn2_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7><br class="">+// CHECK: ret <4 x half> [[SHUFFLE_I]]<br class="">+float16x4_t test_vtrn2_f16(float16x4_t a, float16x4_t b) {<br class="">+ return vtrn2_f16(a, b);<br class="">+}<br class="">+<br class="">+// CHECK-LABEL: @test_vtrn2q_f16(<br class="">+// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15><br class="">+// CHECK: ret <8 x half> [[SHUFFLE_I]]<br class="">+float16x8_t test_vtrn2q_f16(float16x8_t a, float16x8_t b) {<br class="">+ return vtrn2q_f16(a, b);<br class="">+}<br class="">+<br class=""><br class="">Modified: cfe/trunk/utils/TableGen/NeonEmitter.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/NeonEmitter.cpp?rev=304493&r1=304492&r2=304493&view=diff" class="">http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/NeonEmitter.cpp?rev=304493&r1=304492&r2=304493&view=diff</a><br class="">==============================================================================<br class="">--- cfe/trunk/utils/TableGen/NeonEmitter.cpp (original)<br class="">+++ cfe/trunk/utils/TableGen/NeonEmitter.cpp Thu Jun 1 18:22:29 2017<br class="">@@ -860,6 +860,10 @@ void Type::applyModifier(char Mod) {<br class=""> Float = true;<br class=""> ElementBitwidth = 64;<br class=""> break;<br class="">+ case 'H':<br class="">+ Float = true;<br class="">+ ElementBitwidth = 16;<br class="">+ break;<br class=""> case 'g':<br class=""> if (AppliedQuad)<br class=""> Bitwidth /= 2;<br class="">@@ -1006,7 +1010,7 @@ std::string Intrinsic::getInstTypeCode(T<br class=""> }<br class=""><br class=""> static bool isFloatingPointProtoModifier(char Mod) {<br class="">- return Mod == 'F' || Mod == 'f';<br class="">+ return Mod == 'F' || Mod == 'f' || Mod == 'H';<br class=""> }<br class=""><br class=""> std::string Intrinsic::getBuiltinTypeStr() {<br class=""><br class=""><br class="">_______________________________________________<br class="">cfe-commits mailing list<br class=""><a href="mailto:cfe-commits@lists.llvm.org" class="">cfe-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits<br class=""></div></div></blockquote></div><br class=""></div></body></html>