r263048 - ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.
David Blaikie via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 9 13:20:51 PST 2016
If we are touching these tests at all, as a cleanup, why aren't we
adjusting them to not pass through the llvm optimizers/code generators at
all? Generally we are pretty clear that any test in Clang looking at llvms
generated assembly is an anachronism to be removed eventually
On Mar 9, 2016 10:59 AM, "Tim Northover via cfe-commits" <
cfe-commits at lists.llvm.org> wrote:
> Author: tnorthover
> Date: Wed Mar 9 12:54:42 2016
> New Revision: 263048
>
> URL: http://llvm.org/viewvc/llvm-project?rev=263048&view=rev
> Log:
> ARM & AArch64: convert asm tests to LLVM IR and restrict optimizations.
>
> This is mostly a one-time autoconversion of tests that checked assembly
> after
> "-Owhatever" compiles to only run "opt -mem2reg" and check the assembly.
> This
> should make them much more stable to changes in LLVM so they won't break on
> unrelated changes.
>
> "opt -mem2reg" is a compromise designed to increase the readability of
> tests
> that check dataflow, while minimizing dependency on LLVM. Hopefully
> mem2reg is
> stable enough that no surpises will come along.
>
> Should address http://llvm.org/PR26815.
>
> Modified:
> cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
> cfe/trunk/test/CodeGen/aarch64-neon-3v.c
> cfe/trunk/test/CodeGen/aarch64-neon-across.c
> cfe/trunk/test/CodeGen/aarch64-neon-extract.c
> cfe/trunk/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
> cfe/trunk/test/CodeGen/aarch64-neon-fma.c
> cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
> cfe/trunk/test/CodeGen/aarch64-neon-ldst-one.c
> cfe/trunk/test/CodeGen/aarch64-neon-misc.c
> cfe/trunk/test/CodeGen/aarch64-neon-perm.c
> cfe/trunk/test/CodeGen/aarch64-neon-scalar-copy.c
> cfe/trunk/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
> cfe/trunk/test/CodeGen/aarch64-neon-shifts.c
> cfe/trunk/test/CodeGen/aarch64-neon-tbl.c
> cfe/trunk/test/CodeGen/aarch64-neon-vcombine.c
> cfe/trunk/test/CodeGen/aarch64-neon-vget-hilo.c
> cfe/trunk/test/CodeGen/aarch64-neon-vget.c
> cfe/trunk/test/CodeGen/aarch64-poly128.c
> cfe/trunk/test/CodeGen/aarch64-poly64.c
> cfe/trunk/test/CodeGen/arm-bitfield-alignment.c
> cfe/trunk/test/CodeGen/arm-crc32.c
> cfe/trunk/test/CodeGen/arm-neon-directed-rounding.c
> cfe/trunk/test/CodeGen/arm-neon-fma.c
> cfe/trunk/test/CodeGen/arm-neon-numeric-maxmin.c
> cfe/trunk/test/CodeGen/arm-neon-shifts.c
> cfe/trunk/test/CodeGen/arm-neon-vcvtX.c
> cfe/trunk/test/CodeGen/arm-neon-vget.c
> cfe/trunk/test/CodeGen/arm64-be-bitfield.c
> cfe/trunk/test/CodeGen/arm64-crc32.c
> cfe/trunk/test/CodeGen/arm64-lanes.c
> cfe/trunk/test/CodeGen/arm64_vcopy.c
> cfe/trunk/test/CodeGen/arm64_vcreate.c
> cfe/trunk/test/CodeGen/arm64_vdupq_n_f64.c
> cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
> cfe/trunk/test/CodeGen/builtins-arm-exclusive.c
> cfe/trunk/test/CodeGen/builtins-arm.c
> cfe/trunk/test/CodeGen/builtins-arm64.c
> cfe/trunk/test/CodeGen/fp128_complex.c
> cfe/trunk/test/CodeGen/neon-immediate-ubsan.c
>
> Modified: cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
> URL:
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-2velem.c?rev=263048&r1=263047&r2=263048&view=diff
>
> ==============================================================================
> --- cfe/trunk/test/CodeGen/aarch64-neon-2velem.c (original)
> +++ cfe/trunk/test/CodeGen/aarch64-neon-2velem.c Wed Mar 9 12:54:42 2016
> @@ -1,2452 +1,5011 @@
> -// REQUIRES: aarch64-registered-target
> -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S
> -O3 -o - %s | FileCheck %s
> +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon
> -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
>
> // Test new aarch64 intrinsics and types
>
> #include <arm_neon.h>
>
> +// CHECK-LABEL: define <4 x i16> @test_vmla_lane_s16(<4 x i16> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]]
> +// CHECK: ret <4 x i16> [[ADD]]
> int16x4_t test_vmla_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmla_lane_s16
> return vmla_lane_s16(a, b, v, 3);
> - // CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmlaq_lane_s16(<8 x i16> %a, <8 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]]
> +// CHECK: ret <8 x i16> [[ADD]]
> int16x8_t test_vmlaq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlaq_lane_s16
> return vmlaq_lane_s16(a, b, v, 3);
> - // CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmla_lane_s32(<2 x i32> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]]
> +// CHECK: ret <2 x i32> [[ADD]]
> int32x2_t test_vmla_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmla_lane_s32
> return vmla_lane_s32(a, b, v, 1);
> - // CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlaq_lane_s32(<4 x i32> %a, <4 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlaq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlaq_lane_s32
> return vmlaq_lane_s32(a, b, v, 1);
> - // CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmla_laneq_s16(<4 x i16> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <4 x i16> %a, [[MUL]]
> +// CHECK: ret <4 x i16> [[ADD]]
> int16x4_t test_vmla_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmla_laneq_s16
> return vmla_laneq_s16(a, b, v, 7);
> - // CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmlaq_laneq_s16(<8 x i16> %a, <8 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <8 x i16> %a, [[MUL]]
> +// CHECK: ret <8 x i16> [[ADD]]
> int16x8_t test_vmlaq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlaq_laneq_s16
> return vmlaq_laneq_s16(a, b, v, 7);
> - // CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmla_laneq_s32(<2 x i32> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <2 x i32> %a, [[MUL]]
> +// CHECK: ret <2 x i32> [[ADD]]
> int32x2_t test_vmla_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmla_laneq_s32
> return vmla_laneq_s32(a, b, v, 3);
> - // CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlaq_laneq_s32(<4 x i32> %a, <4 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[MUL]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlaq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlaq_laneq_s32
> return vmlaq_laneq_s32(a, b, v, 3);
> - // CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmls_lane_s16(<4 x i16> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]]
> +// CHECK: ret <4 x i16> [[SUB]]
> int16x4_t test_vmls_lane_s16(int16x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmls_lane_s16
> return vmls_lane_s16(a, b, v, 3);
> - // CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmlsq_lane_s16(<8 x i16> %a, <8 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]]
> +// CHECK: ret <8 x i16> [[SUB]]
> int16x8_t test_vmlsq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlsq_lane_s16
> return vmlsq_lane_s16(a, b, v, 3);
> - // CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmls_lane_s32(<2 x i32> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]]
> +// CHECK: ret <2 x i32> [[SUB]]
> int32x2_t test_vmls_lane_s32(int32x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmls_lane_s32
> return vmls_lane_s32(a, b, v, 1);
> - // CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsq_lane_s32(<4 x i32> %a, <4 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlsq_lane_s32
> return vmlsq_lane_s32(a, b, v, 1);
> - // CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmls_laneq_s16(<4 x i16> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <4 x i16> %a, [[MUL]]
> +// CHECK: ret <4 x i16> [[SUB]]
> int16x4_t test_vmls_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmls_laneq_s16
> return vmls_laneq_s16(a, b, v, 7);
> - // CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmlsq_laneq_s16(<8 x i16> %a, <8 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <8 x i16> %a, [[MUL]]
> +// CHECK: ret <8 x i16> [[SUB]]
> int16x8_t test_vmlsq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlsq_laneq_s16
> return vmlsq_laneq_s16(a, b, v, 7);
> - // CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmls_laneq_s32(<2 x i32> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <2 x i32> %a, [[MUL]]
> +// CHECK: ret <2 x i32> [[SUB]]
> int32x2_t test_vmls_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmls_laneq_s32
> return vmls_laneq_s32(a, b, v, 3);
> - // CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsq_laneq_s32(<4 x i32> %a, <4 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %b, [[SHUFFLE]]
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[MUL]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlsq_laneq_s32
> return vmlsq_laneq_s32(a, b, v, 3);
> - // CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmul_lane_s16(<4 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i16> [[MUL]]
> int16x4_t test_vmul_lane_s16(int16x4_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vmul_lane_s16
> return vmul_lane_s16(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_s16(<8 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <8 x i16> [[MUL]]
> int16x8_t test_vmulq_lane_s16(int16x8_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vmulq_lane_s16
> return vmulq_lane_s16(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmul_lane_s32(<2 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <2 x i32> [[MUL]]
> int32x2_t test_vmul_lane_s32(int32x2_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vmul_lane_s32
> return vmul_lane_s32(a, v, 1);
> - // CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_s32(<4 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i32> [[MUL]]
> int32x4_t test_vmulq_lane_s32(int32x4_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vmulq_lane_s32
> return vmulq_lane_s32(a, v, 1);
> - // CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmul_lane_u16(<4 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i16> [[MUL]]
> uint16x4_t test_vmul_lane_u16(uint16x4_t a, uint16x4_t v) {
> - // CHECK-LABEL: test_vmul_lane_u16
> return vmul_lane_u16(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmulq_lane_u16(<8 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <8 x i16> [[MUL]]
> uint16x8_t test_vmulq_lane_u16(uint16x8_t a, uint16x4_t v) {
> - // CHECK-LABEL: test_vmulq_lane_u16
> return vmulq_lane_u16(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmul_lane_u32(<2 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <2 x i32> [[MUL]]
> uint32x2_t test_vmul_lane_u32(uint32x2_t a, uint32x2_t v) {
> - // CHECK-LABEL: test_vmul_lane_u32
> return vmul_lane_u32(a, v, 1);
> - // CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmulq_lane_u32(<4 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i32> [[MUL]]
> uint32x4_t test_vmulq_lane_u32(uint32x4_t a, uint32x2_t v) {
> - // CHECK-LABEL: test_vmulq_lane_u32
> return vmulq_lane_u32(a, v, 1);
> - // CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_s16(<4 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i16> [[MUL]]
> int16x4_t test_vmul_laneq_s16(int16x4_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vmul_laneq_s16
> return vmul_laneq_s16(a, v, 7);
> - // CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_s16(<8 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <8 x i16> [[MUL]]
> int16x8_t test_vmulq_laneq_s16(int16x8_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vmulq_laneq_s16
> return vmulq_laneq_s16(a, v, 7);
> - // CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_s32(<2 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <2 x i32> [[MUL]]
> int32x2_t test_vmul_laneq_s32(int32x2_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vmul_laneq_s32
> return vmul_laneq_s32(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_s32(<4 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i32> [[MUL]]
> int32x4_t test_vmulq_laneq_s32(int32x4_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vmulq_laneq_s32
> return vmulq_laneq_s32(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vmul_laneq_u16(<4 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <4 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i16> [[MUL]]
> uint16x4_t test_vmul_laneq_u16(uint16x4_t a, uint16x8_t v) {
> - // CHECK-LABEL: test_vmul_laneq_u16
> return vmul_laneq_u16(a, v, 7);
> - // CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <8 x i16> @test_vmulq_laneq_u16(<8 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[MUL:%.*]] = mul <8 x i16> %a, [[SHUFFLE]]
> +// CHECK: ret <8 x i16> [[MUL]]
> uint16x8_t test_vmulq_laneq_u16(uint16x8_t a, uint16x8_t v) {
> - // CHECK-LABEL: test_vmulq_laneq_u16
> return vmulq_laneq_u16(a, v, 7);
> - // CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i32> @test_vmul_laneq_u32(<2 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <2 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <2 x i32> [[MUL]]
> uint32x2_t test_vmul_laneq_u32(uint32x2_t a, uint32x4_t v) {
> - // CHECK-LABEL: test_vmul_laneq_u32
> return vmul_laneq_u32(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmulq_laneq_u32(<4 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[MUL:%.*]] = mul <4 x i32> %a, [[SHUFFLE]]
> +// CHECK: ret <4 x i32> [[MUL]]
> uint32x4_t test_vmulq_laneq_u32(uint32x4_t a, uint32x4_t v) {
> - // CHECK-LABEL: test_vmulq_laneq_u32
> return vmulq_laneq_u32(a, v, 3);
> - // CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <2 x float> @test_vfma_lane_f32(<2 x float> %a, <2
> x float> %b, <2 x float> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x
> float> [[TMP3]], <2 x i32> <i32 1, i32 1>
> +// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
> +// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
> +// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float>
> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA]]1)
> +// CHECK: ret <2 x float> [[FMLA]]2
> float32x2_t test_vfma_lane_f32(float32x2_t a, float32x2_t b, float32x2_t
> v) {
> - // CHECK-LABEL: test_vfma_lane_f32
> return vfma_lane_f32(a, b, v, 1);
> - // CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x float> @test_vfmaq_lane_f32(<4 x float> %a,
> <4 x float> %b, <2 x float> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %v to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x
> float> [[TMP3]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
> +// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float>
> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA]]1)
> +// CHECK: ret <4 x float> [[FMLA]]2
> float32x4_t test_vfmaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t
> v) {
> - // CHECK-LABEL: test_vfmaq_lane_f32
> return vfmaq_lane_f32(a, b, v, 1);
> - // CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <2 x float> @test_vfma_laneq_f32(<2 x float> %a,
> <2 x float> %b, <4 x float> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x
> float> [[TMP5]], <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float>
> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]])
> +// CHECK: ret <2 x float> [[TMP6]]
> float32x2_t test_vfma_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t
> v) {
> - // CHECK-LABEL: test_vfma_laneq_f32
> return vfma_laneq_f32(a, b, v, 3);
> - // CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x float> @test_vfmaq_laneq_f32(<4 x float> %a,
> <4 x float> %b, <4 x float> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %v to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x
> float> [[TMP5]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float>
> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]])
> +// CHECK: ret <4 x float> [[TMP6]]
> float32x4_t test_vfmaq_laneq_f32(float32x4_t a, float32x4_t b,
> float32x4_t v) {
> - // CHECK-LABEL: test_vfmaq_laneq_f32
> return vfmaq_laneq_f32(a, b, v, 3);
> - // CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <2 x float> @test_vfms_lane_f32(<2 x float> %a, <2
> x float> %b, <2 x float> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float
> -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x
> float> [[TMP3]], <2 x i32> <i32 1, i32 1>
> +// CHECK: [[FMLA:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
> +// CHECK: [[FMLA1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
> +// CHECK: [[FMLA2:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float>
> [[FMLA]], <2 x float> [[LANE]], <2 x float> [[FMLA]]1)
> +// CHECK: ret <2 x float> [[FMLA]]2
> float32x2_t test_vfms_lane_f32(float32x2_t a, float32x2_t b, float32x2_t
> v) {
> - // CHECK-LABEL: test_vfms_lane_f32
> return vfms_lane_f32(a, b, v, 1);
> - // CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x float> @test_vfmsq_lane_f32(<4 x float> %a,
> <4 x float> %b, <2 x float> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <2 x float> <float -0.000000e+00, float
> -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x float> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x
> float> [[TMP3]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
> +// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
> +// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[FMLA2:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float>
> [[FMLA]], <4 x float> [[LANE]], <4 x float> [[FMLA]]1)
> +// CHECK: ret <4 x float> [[FMLA]]2
> float32x4_t test_vfmsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t
> v) {
> - // CHECK-LABEL: test_vfmsq_lane_f32
> return vfmsq_lane_f32(a, b, v, 1);
> - // CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <2 x float> @test_vfms_laneq_f32(<2 x float> %a,
> <2 x float> %b, <4 x float> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float
> -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
> +// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x
> float> [[TMP5]], <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float>
> [[LANE]], <2 x float> [[TMP4]], <2 x float> [[TMP3]])
> +// CHECK: ret <2 x float> [[TMP6]]
> float32x2_t test_vfms_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t
> v) {
> - // CHECK-LABEL: test_vfms_laneq_f32
> return vfms_laneq_f32(a, b, v, 3);
> - // CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x float> @test_vfmsq_laneq_f32(<4 x float> %a,
> <4 x float> %b, <4 x float> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float
> -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
> +// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x
> float> [[TMP5]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float>
> [[LANE]], <4 x float> [[TMP4]], <4 x float> [[TMP3]])
> +// CHECK: ret <4 x float> [[TMP6]]
> float32x4_t test_vfmsq_laneq_f32(float32x4_t a, float32x4_t b,
> float32x4_t v) {
> - // CHECK-LABEL: test_vfmsq_laneq_f32
> return vfmsq_laneq_f32(a, b, v, 3);
> - // CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <2 x double> @test_vfmaq_lane_f64(<2 x double> %a,
> <2 x double> %b, <1 x double> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
> +// CHECK: [[LANE:%.*]] = shufflevector <1 x double> [[TMP3]], <1 x
> double> [[TMP3]], <2 x i32> zeroinitializer
> +// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
> +// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
> +// CHECK: [[FMLA2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x
> double> [[FMLA]], <2 x double> [[LANE]], <2 x double> [[FMLA]]1)
> +// CHECK: ret <2 x double> [[FMLA]]2
> float64x2_t test_vfmaq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t
> v) {
> - // CHECK-LABEL: test_vfmaq_lane_f64
> return vfmaq_lane_f64(a, b, v, 0);
> - // CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
> }
>
> +// CHECK-LABEL: define <2 x double> @test_vfmaq_laneq_f64(<2 x double>
> %a, <2 x double> %b, <2 x double> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x
> double> [[TMP5]], <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double>
> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]])
> +// CHECK: ret <2 x double> [[TMP6]]
> float64x2_t test_vfmaq_laneq_f64(float64x2_t a, float64x2_t b,
> float64x2_t v) {
> - // CHECK-LABEL: test_vfmaq_laneq_f64
> return vfmaq_laneq_f64(a, b, v, 1);
> - // CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
> }
>
> +// CHECK-LABEL: define <2 x double> @test_vfmsq_lane_f64(<2 x double> %a,
> <2 x double> %b, <1 x double> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <1 x double> <double -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x double>
> +// CHECK: [[LANE:%.*]] = shufflevector <1 x double> [[TMP3]], <1 x
> double> [[TMP3]], <2 x i32> zeroinitializer
> +// CHECK: [[FMLA:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
> +// CHECK: [[FMLA1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
> +// CHECK: [[FMLA2:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x
> double> [[FMLA]], <2 x double> [[LANE]], <2 x double> [[FMLA]]1)
> +// CHECK: ret <2 x double> [[FMLA]]2
> float64x2_t test_vfmsq_lane_f64(float64x2_t a, float64x2_t b, float64x1_t
> v) {
> - // CHECK-LABEL: test_vfmsq_lane_f64
> return vfmsq_lane_f64(a, b, v, 0);
> - // CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
> }
>
> +// CHECK-LABEL: define <2 x double> @test_vfmsq_laneq_f64(<2 x double>
> %a, <2 x double> %b, <2 x double> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <2 x double> <double -0.000000e+00, double
> -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
> +// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
> +// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
> +// CHECK: [[LANE:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x
> double> [[TMP5]], <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double>
> [[LANE]], <2 x double> [[TMP4]], <2 x double> [[TMP3]])
> +// CHECK: ret <2 x double> [[TMP6]]
> float64x2_t test_vfmsq_laneq_f64(float64x2_t a, float64x2_t b,
> float64x2_t v) {
> - // CHECK-LABEL: test_vfmsq_laneq_f64
> return vfmsq_laneq_f64(a, b, v, 1);
> - // CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
> }
>
> +// CHECK-LABEL: define float @test_vfmas_laneq_f32(float %a, float %b, <4
> x float> %v) #0 {
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %v to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[EXTRACT:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
> +// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float %b, float
> [[EXTRACT]], float %a)
> +// CHECK: ret float [[TMP2]]
> float32_t test_vfmas_laneq_f32(float32_t a, float32_t b, float32x4_t v) {
> - // CHECK-LABEL: test_vfmas_laneq_f32
> return vfmas_laneq_f32(a, b, v, 3);
> - // CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define double @test_vfmsd_lane_f64(double %a, double %b,
> <1 x double> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <1 x double> <double -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
> +// CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> [[TMP1]], i32 0
> +// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double
> [[EXTRACT]], double %a)
> +// CHECK: ret double [[TMP2]]
> float64_t test_vfmsd_lane_f64(float64_t a, float64_t b, float64x1_t v) {
> - // CHECK-LABEL: test_vfmsd_lane_f64
> return vfmsd_lane_f64(a, b, v, 0);
> - // CHECK: {{fmls d[0-9]+, d[0-9]+, v[0-9]+\.d\[0\]|fmsub d[0-9]+,
> d[0-9]+, d[0-9]+}}
> }
>
> +// CHECK-LABEL: define float @test_vfmss_laneq_f32(float %a, float %b, <4
> x float> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <4 x float> <float -0.000000e+00, float
> -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
> +// CHECK: [[EXTRACT:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
> +// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float %b, float
> [[EXTRACT]], float %a)
> +// CHECK: ret float [[TMP2]]
> float32_t test_vfmss_laneq_f32(float32_t a, float32_t b, float32x4_t v) {
> - // CHECK-LABEL: test_vfmss_laneq_f32
> return vfmss_laneq_f32(a, b, v, 3);
> - // CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define double @test_vfmsd_laneq_f64(double %a, double %b,
> <2 x double> %v) #0 {
> +// CHECK: [[SUB:%.*]] = fsub <2 x double> <double -0.000000e+00, double
> -0.000000e+00>, %v
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x double> [[SUB]] to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
> +// CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
> +// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double
> [[EXTRACT]], double %a)
> +// CHECK: ret double [[TMP2]]
> float64_t test_vfmsd_laneq_f64(float64_t a, float64_t b, float64x2_t v) {
> - // CHECK-LABEL: test_vfmsd_laneq_f64
> return vfmsd_laneq_f64(a, b, v, 1);
> - // CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_s16(<4 x i32> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlal_lane_s16
> return vmlal_lane_s16(a, b, v, 3);
> - // CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_s32(<2 x i64> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlal_lane_s32
> return vmlal_lane_s32(a, b, v, 1);
> - // CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_s16(<4 x i32> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlal_laneq_s16
> return vmlal_laneq_s16(a, b, v, 7);
> - // CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_s32(<2 x i64> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlal_laneq_s32
> return vmlal_laneq_s32(a, b, v, 3);
> - // CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_s16(<4 x i32> %a,
> <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v)
> {
> - // CHECK-LABEL: test_vmlal_high_lane_s16
> return vmlal_high_lane_s16(a, b, v, 3);
> - // CHECK: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_s32(<2 x i64> %a,
> <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v)
> {
> - // CHECK-LABEL: test_vmlal_high_lane_s32
> return vmlal_high_lane_s32(a, b, v, 1);
> - // CHECK: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_s16(<4 x i32> %a,
> <8 x i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t
> v) {
> - // CHECK-LABEL: test_vmlal_high_laneq_s16
> return vmlal_high_laneq_s16(a, b, v, 7);
> - // CHECK: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_s32(<2 x i64> %a,
> <4 x i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t
> v) {
> - // CHECK-LABEL: test_vmlal_high_laneq_s32
> return vmlal_high_laneq_s32(a, b, v, 3);
> - // CHECK: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_s16(<4 x i32> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlsl_lane_s16
> return vmlsl_lane_s16(a, b, v, 3);
> - // CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_s32(<2 x i64> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlsl_lane_s32
> return vmlsl_lane_s32(a, b, v, 1);
> - // CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_s16(<4 x i32> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_laneq_s16(int32x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlsl_laneq_s16
> return vmlsl_laneq_s16(a, b, v, 7);
> - // CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_s32(<2 x i64> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_laneq_s32(int64x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlsl_laneq_s32
> return vmlsl_laneq_s32(a, b, v, 3);
> - // CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_s16(<4 x i32> %a,
> <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t v)
> {
> - // CHECK-LABEL: test_vmlsl_high_lane_s16
> return vmlsl_high_lane_s16(a, b, v, 3);
> - // CHECK: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_s32(<2 x i64> %a,
> <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t v)
> {
> - // CHECK-LABEL: test_vmlsl_high_lane_s32
> return vmlsl_high_lane_s32(a, b, v, 1);
> - // CHECK: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_s16(<4 x i32> %a,
> <8 x i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_high_laneq_s16(int32x4_t a, int16x8_t b, int16x8_t
> v) {
> - // CHECK-LABEL: test_vmlsl_high_laneq_s16
> return vmlsl_high_laneq_s16(a, b, v, 7);
> - // CHECK: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_s32(<2 x i64> %a,
> <4 x i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_high_laneq_s32(int64x2_t a, int32x4_t b, int32x4_t
> v) {
> - // CHECK-LABEL: test_vmlsl_high_laneq_s32
> return vmlsl_high_laneq_s32(a, b, v, 3);
> - // CHECK: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_lane_u16(<4 x i32> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_lane_u16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlal_lane_u16
> return vmlal_lane_u16(a, b, v, 3);
> - // CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_lane_u32(<2 x i64> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_lane_u32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlal_lane_u32
> return vmlal_lane_u32(a, b, v, 1);
> - // CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_laneq_u16(<4 x i32> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_laneq_u16(int32x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlal_laneq_u16
> return vmlal_laneq_u16(a, b, v, 7);
> - // CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_laneq_u32(<2 x i64> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_laneq_u32(int64x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlal_laneq_u32
> return vmlal_laneq_u32(a, b, v, 3);
> - // CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_high_lane_u16(<4 x i32> %a,
> <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_high_lane_u16(int32x4_t a, int16x8_t b, int16x4_t v)
> {
> - // CHECK-LABEL: test_vmlal_high_lane_u16
> return vmlal_high_lane_u16(a, b, v, 3);
> - // CHECK: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_high_lane_u32(<2 x i64> %a,
> <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_high_lane_u32(int64x2_t a, int32x4_t b, int32x2_t v)
> {
> - // CHECK-LABEL: test_vmlal_high_lane_u32
> return vmlal_high_lane_u32(a, b, v, 1);
> - // CHECK: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlal_high_laneq_u16(<4 x i32> %a,
> <8 x i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[ADD]]
> int32x4_t test_vmlal_high_laneq_u16(int32x4_t a, int16x8_t b, int16x8_t
> v) {
> - // CHECK-LABEL: test_vmlal_high_laneq_u16
> return vmlal_high_laneq_u16(a, b, v, 7);
> - // CHECK: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlal_high_laneq_u32(<2 x i64> %a,
> <4 x i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[ADD:%.*]] = add <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[ADD]]
> int64x2_t test_vmlal_high_laneq_u32(int64x2_t a, int32x4_t b, int32x4_t
> v) {
> - // CHECK-LABEL: test_vmlal_high_laneq_u32
> return vmlal_high_laneq_u32(a, b, v, 3);
> - // CHECK: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_lane_u16(<4 x i32> %a, <4 x
> i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_lane_u16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vmlsl_lane_u16
> return vmlsl_lane_u16(a, b, v, 3);
> - // CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_lane_u32(<2 x i64> %a, <2 x
> i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_lane_u32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vmlsl_lane_u32
> return vmlsl_lane_u32(a, b, v, 1);
> - // CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_laneq_u16(<4 x i32> %a, <4 x
> i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_laneq_u16(int32x4_t a, int16x4_t b, int16x8_t v) {
> - // CHECK-LABEL: test_vmlsl_laneq_u16
> return vmlsl_laneq_u16(a, b, v, 7);
> - // CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_laneq_u32(<2 x i64> %a, <2 x
> i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_laneq_u32(int64x2_t a, int32x2_t b, int32x4_t v) {
> - // CHECK-LABEL: test_vmlsl_laneq_u32
> return vmlsl_laneq_u32(a, b, v, 3);
> - // CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_lane_u16(<4 x i32> %a,
> <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_high_lane_u16(int32x4_t a, int16x8_t b, int16x4_t v)
> {
> - // CHECK-LABEL: test_vmlsl_high_lane_u16
> return vmlsl_high_lane_u16(a, b, v, 3);
> - // CHECK: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_lane_u32(<2 x i64> %a,
> <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_high_lane_u32(int64x2_t a, int32x4_t b, int32x2_t v)
> {
> - // CHECK-LABEL: test_vmlsl_high_lane_u32
> return vmlsl_high_lane_u32(a, b, v, 1);
> - // CHECK: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmlsl_high_laneq_u16(<4 x i32> %a,
> <8 x i16> %b, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <4 x i32> %a, [[VMULL2_I]]
> +// CHECK: ret <4 x i32> [[SUB]]
> int32x4_t test_vmlsl_high_laneq_u16(int32x4_t a, int16x8_t b, int16x8_t
> v) {
> - // CHECK-LABEL: test_vmlsl_high_laneq_u16
> return vmlsl_high_laneq_u16(a, b, v, 7);
> - // CHECK: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmlsl_high_laneq_u32(<2 x i64> %a,
> <4 x i32> %b, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: [[SUB:%.*]] = sub <2 x i64> %a, [[VMULL2_I]]
> +// CHECK: ret <2 x i64> [[SUB]]
> int64x2_t test_vmlsl_high_laneq_u32(int64x2_t a, int32x4_t b, int32x4_t
> v) {
> - // CHECK-LABEL: test_vmlsl_high_laneq_u32
> return vmlsl_high_laneq_u32(a, b, v, 3);
> - // CHECK: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_lane_s16(<4 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> int32x4_t test_vmull_lane_s16(int16x4_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vmull_lane_s16
> return vmull_lane_s16(a, v, 3);
> - // CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_lane_s32(<2 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> int64x2_t test_vmull_lane_s32(int32x2_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vmull_lane_s32
> return vmull_lane_s32(a, v, 1);
> - // CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_lane_u16(<4 x i16> %a, <4 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> uint32x4_t test_vmull_lane_u16(uint16x4_t a, uint16x4_t v) {
> - // CHECK-LABEL: test_vmull_lane_u16
> return vmull_lane_u16(a, v, 3);
> - // CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_lane_u32(<2 x i32> %a, <2 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> uint64x2_t test_vmull_lane_u32(uint32x2_t a, uint32x2_t v) {
> - // CHECK-LABEL: test_vmull_lane_u32
> return vmull_lane_u32(a, v, 1);
> - // CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_s16(<8 x i16> %a,
> <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> int32x4_t test_vmull_high_lane_s16(int16x8_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vmull_high_lane_s16
> return vmull_high_lane_s16(a, v, 3);
> - // CHECK: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_s32(<4 x i32> %a,
> <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> int64x2_t test_vmull_high_lane_s32(int32x4_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vmull_high_lane_s32
> return vmull_high_lane_s32(a, v, 1);
> - // CHECK: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_high_lane_u16(<8 x i16> %a,
> <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> uint32x4_t test_vmull_high_lane_u16(uint16x8_t a, uint16x4_t v) {
> - // CHECK-LABEL: test_vmull_high_lane_u16
> return vmull_high_lane_u16(a, v, 3);
> - // CHECK: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_high_lane_u32(<4 x i32> %a,
> <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> uint64x2_t test_vmull_high_lane_u32(uint32x4_t a, uint32x2_t v) {
> - // CHECK-LABEL: test_vmull_high_lane_u32
> return vmull_high_lane_u32(a, v, 1);
> - // CHECK: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_s16(<4 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> int32x4_t test_vmull_laneq_s16(int16x4_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vmull_laneq_s16
> return vmull_laneq_s16(a, v, 7);
> - // CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_s32(<2 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> int64x2_t test_vmull_laneq_s32(int32x2_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vmull_laneq_s32
> return vmull_laneq_s32(a, v, 3);
> - // CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_laneq_u16(<4 x i16> %a, <8 x
> i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> uint32x4_t test_vmull_laneq_u16(uint16x4_t a, uint16x8_t v) {
> - // CHECK-LABEL: test_vmull_laneq_u16
> return vmull_laneq_u16(a, v, 7);
> - // CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_laneq_u32(<2 x i32> %a, <4 x
> i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> uint64x2_t test_vmull_laneq_u32(uint32x2_t a, uint32x4_t v) {
> - // CHECK-LABEL: test_vmull_laneq_u32
> return vmull_laneq_u32(a, v, 3);
> - // CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_s16(<8 x i16> %a,
> <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> int32x4_t test_vmull_high_laneq_s16(int16x8_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vmull_high_laneq_s16
> return vmull_high_laneq_s16(a, v, 7);
> - // CHECK: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_s32(<4 x i32> %a,
> <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> int64x2_t test_vmull_high_laneq_s32(int32x4_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vmull_high_laneq_s32
> return vmull_high_laneq_s32(a, v, 3);
> - // CHECK: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vmull_high_laneq_u16(<8 x i16> %a,
> <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VMULL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16>
> [[VMULL1_I]]) #2
> +// CHECK: ret <4 x i32> [[VMULL2_I]]
> uint32x4_t test_vmull_high_laneq_u16(uint16x8_t a, uint16x8_t v) {
> - // CHECK-LABEL: test_vmull_high_laneq_u16
> return vmull_high_laneq_u16(a, v, 7);
> - // CHECK: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vmull_high_laneq_u32(<4 x i32> %a,
> <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VMULL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32>
> [[VMULL1_I]]) #2
> +// CHECK: ret <2 x i64> [[VMULL2_I]]
> uint64x2_t test_vmull_high_laneq_u32(uint32x4_t a, uint32x4_t v) {
> - // CHECK-LABEL: test_vmull_high_laneq_u32
> return vmull_high_laneq_u32(a, v, 3);
> - // CHECK: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmlal_lane_s16(<4 x i32> %a, <4
> x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
> +// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]]
> int32x4_t test_vqdmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vqdmlal_lane_s16
> return vqdmlal_lane_s16(a, b, v, 3);
> - // CHECK: sqdmlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmlal_lane_s32(<2 x i64> %a, <2
> x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
> +// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]]
> int64x2_t test_vqdmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vqdmlal_lane_s32
> return vqdmlal_lane_s32(a, b, v, 1);
> - // CHECK: sqdmlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmlal_high_lane_s16(<4 x i32>
> %a, <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
> +// CHECK: [[VQDMLAL_V3_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[VQDMLAL_V_I]], <4 x i32>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <4 x i32> [[VQDMLAL_V3_I]]
> int32x4_t test_vqdmlal_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t
> v) {
> - // CHECK-LABEL: test_vqdmlal_high_lane_s16
> return vqdmlal_high_lane_s16(a, b, v, 3);
> - // CHECK: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmlal_high_lane_s32(<2 x i64>
> %a, <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLAL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
> +// CHECK: [[VQDMLAL_V3_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[VQDMLAL_V_I]], <2 x i64>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <2 x i64> [[VQDMLAL_V3_I]]
> int64x2_t test_vqdmlal_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t
> v) {
> - // CHECK-LABEL: test_vqdmlal_high_lane_s32
> return vqdmlal_high_lane_s32(a, b, v, 1);
> - // CHECK: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_lane_s16(<4 x i32> %a, <4
> x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
> +// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]]
> int32x4_t test_vqdmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t v) {
> - // CHECK-LABEL: test_vqdmlsl_lane_s16
> return vqdmlsl_lane_s16(a, b, v, 3);
> - // CHECK: sqdmlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_lane_s32(<2 x i64> %a, <2
> x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
> +// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]]
> int64x2_t test_vqdmlsl_lane_s32(int64x2_t a, int32x2_t b, int32x2_t v) {
> - // CHECK-LABEL: test_vqdmlsl_lane_s32
> return vqdmlsl_lane_s32(a, b, v, 1);
> - // CHECK: sqdmlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmlsl_high_lane_s16(<4 x i32>
> %a, <8 x i16> %b, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %b, <8 x i16> %b,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMLAL_I]], <4 x i16>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
> +// CHECK: [[VQDMLSL_V3_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[VQDMLSL_V_I]], <4 x i32>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <4 x i32> [[VQDMLSL_V3_I]]
> int32x4_t test_vqdmlsl_high_lane_s16(int32x4_t a, int16x8_t b, int16x4_t
> v) {
> - // CHECK-LABEL: test_vqdmlsl_high_lane_s16
> return vqdmlsl_high_lane_s16(a, b, v, 3);
> - // CHECK: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmlsl_high_lane_s32(<2 x i64>
> %a, <4 x i32> %b, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %b, <4 x i32> %b,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMLAL_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMLAL1_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x i32>
> +// CHECK: [[VQDMLAL2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMLAL_I]], <2 x i32>
> [[VQDMLAL1_I]]) #2
> +// CHECK: [[VQDMLSL_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
> +// CHECK: [[VQDMLSL_V3_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[VQDMLSL_V_I]], <2 x i64>
> [[VQDMLAL2_I]]) #2
> +// CHECK: ret <2 x i64> [[VQDMLSL_V3_I]]
> int64x2_t test_vqdmlsl_high_lane_s32(int64x2_t a, int32x4_t b, int32x2_t
> v) {
> - // CHECK-LABEL: test_vqdmlsl_high_lane_s32
> return vqdmlsl_high_lane_s32(a, b, v, 1);
> - // CHECK: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmull_lane_s16(<4 x i16> %a, <4
> x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>
> +// CHECK: ret <4 x i32> [[TMP2]]
> int32x4_t test_vqdmull_lane_s16(int16x4_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vqdmull_lane_s16
> return vqdmull_lane_s16(a, v, 3);
> - // CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmull_lane_s32(<2 x i32> %a, <2
> x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>
> +// CHECK: ret <2 x i64> [[TMP2]]
> int64x2_t test_vqdmull_lane_s32(int32x2_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vqdmull_lane_s32
> return vqdmull_lane_s32(a, v, 1);
> - // CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmull_laneq_s16(<4 x i16> %a, <8
> x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>
> +// CHECK: ret <4 x i32> [[TMP2]]
> int32x4_t test_vqdmull_laneq_s16(int16x4_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vqdmull_laneq_s16
> return vqdmull_laneq_s16(a, v, 3);
> - // CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmull_laneq_s32(<2 x i32> %a, <4
> x i32> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>
> +// CHECK: ret <2 x i64> [[TMP2]]
> int64x2_t test_vqdmull_laneq_s32(int32x2_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vqdmull_laneq_s32
> return vqdmull_laneq_s32(a, v, 3);
> - // CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_lane_s16(<8 x i16>
> %a, <4 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>
> +// CHECK: ret <4 x i32> [[TMP2]]
> int32x4_t test_vqdmull_high_lane_s16(int16x8_t a, int16x4_t v) {
> - // CHECK-LABEL: test_vqdmull_high_lane_s16
> return vqdmull_high_lane_s16(a, v, 3);
> - // CHECK: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_lane_s32(<4 x i32>
> %a, <2 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> %v, <2 x i32> %v,
> <2 x i32> <i32 1, i32 1>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>
> +// CHECK: ret <2 x i64> [[TMP2]]
> int64x2_t test_vqdmull_high_lane_s32(int32x4_t a, int32x2_t v) {
> - // CHECK-LABEL: test_vqdmull_high_lane_s32
> return vqdmull_high_lane_s32(a, v, 1);
> - // CHECK: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
> }
>
> +// CHECK-LABEL: define <4 x i32> @test_vqdmull_high_laneq_s16(<8 x i16>
> %a, <8 x i16> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a,
> <4 x i32> <i32 4, i32 5, i32 6, i32 7>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <8 x i16> %v, <8 x i16> %v,
> <4 x i32> <i32 7, i32 7, i32 7, i32 7>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <4 x i32>
> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[VQDMULL_V_I]], <4 x i16>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <4 x i32> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <4 x i32>
> +// CHECK: ret <4 x i32> [[TMP2]]
> int32x4_t test_vqdmull_high_laneq_s16(int16x8_t a, int16x8_t v) {
> - // CHECK-LABEL: test_vqdmull_high_laneq_s16
> return vqdmull_high_laneq_s16(a, v, 7);
> - // CHECK: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]
> }
>
> +// CHECK-LABEL: define <2 x i64> @test_vqdmull_high_laneq_s32(<4 x i32>
> %a, <4 x i32> %v) #0 {
> +// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a,
> <2 x i32> <i32 2, i32 3>
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> %v, <4 x i32> %v,
> <2 x i32> <i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULL_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
> +// CHECK: [[VQDMULL_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32>
> +// CHECK: [[VQDMULL_V2_I:%.*]] = call <2 x i64>
> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[VQDMULL_V_I]], <2 x i32>
> [[VQDMULL_V1_I]]) #2
> +// CHECK: [[VQDMULL_V3_I:%.*]] = bitcast <2 x i64> [[VQDMULL_V2_I]] to
> <16 x i8>
> +// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VQDMULL_V3_I]] to <2 x i64>
> +// CHECK: ret <2 x i64> [[TMP2]]
> int64x2_t test_vqdmull_high_laneq_s32(int32x4_t a, int32x4_t v) {
> - // CHECK-LABEL: test_vqdmull_high_laneq_s32
> return vqdmull_high_laneq_s32(a, v, 3);
> - // CHECK: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]
> }
>
> +// CHECK-LABEL: define <4 x i16> @test_vqdmulh_lane_s16(<4 x i16> %a, <4
> x i16> %v) #0 {
> +// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i16> %v, <4 x i16> %v,
> <4 x i32> <i32 3, i32 3, i32 3, i32 3>
> +// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
> +// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE]] to <8 x i8>
> +// CHECK: [[VQDMULH_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
> +// CHECK: [[VQDMULH_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
> +// CHECK: [[VQDMULH_V2_I:%.*]] = call <4 x i16>
> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[VQDMULH_V_I]], <4 x i16>
> [[VQDMULH_V1_I]]) #2
> +// CHECK: [[VQDMULH_V3_I:%.*]] = bitcast <4 x i16> [[VQDMULH_V2_I]] to
> <8 x i8>
> +// CHECK: [[TMP2...
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