[PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post - LLVM

[Tim Northover]

> As I mentioned previously in this email thread, the scenario for this case
> is different from table lookup. We do have instruction directly map to this
> intrinsic directly. The operand conversion between 64-bit and 128-bit should
> be able to be solved by EXTRACT_SUBREG and SUBREG_TO_REG,

It certainly *can* be, and my complaint isn't about that. I love
EXTRACT and friends since they're often free! My complaint is that
we're effectively introducing an unnecessary set of intrinsics (OK, so
they have the same base name as ones that are more useful[*], but
they're still extra backend burden) for something that's representable
at the IR level.

Cheers.

Tim.

[*] Though, now that I think of it, even those ought to be expressible
as IR. Something for the future, I suppose.