[PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post - LLVM

[Jiangning Liu]

Hi Tim,

As I mentioned previously in this email thread, the scenario for this case
is different from table lookup. We do have instruction directly map to this
intrinsic directly. The operand conversion between 64-bit and 128-bit
should be able to be solved by EXTRACT_SUBREG and SUBREG_TO_REG, and we do
have a lot of precedents using them in .td file. Although we are using them
in .cpp file, I don't think it is different from our usage in .td file.

Thanks,
-Jiangning


2013/11/21 Tim Northover <t.p.northover at gmail.com>

> Hi Hao,
>
> Sorry for the delay replying to this one.
>
> > I have implemented in the front-end for vld2_lane. But I'm not sure
> whether the solution is correct. There are many shufflevectors, because we
> need to transfer the input from 64bit vector to 128bit, and also transfer
> the output from 128bit to 64bit.
>
> Yep. But, importantly, the optimiser can see through those
> shufflevectors if it needs to: without them you're just hiding the
> complexity in one monolithic intrinsic for an instruction that doesn't
> even exist really.
>
> The Clang code looks like it's doing roughly what I'd expect, though
> the LLVM code still handles the odd cases -- I assume removing that
> will be part of finishing.
>
> Cheers.
>
> Tim.
>



-- 
Thanks,
-Jiangning
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