[PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post

Hao Liu Hao.Liu at arm.com
Mon Nov 18 18:40:35 PST 2013


Hi Jiangning,

Committed in r195078 http://llvm.org/viewvc/llvm-project?rev=195078&view=rev
and r195079 http://llvm.org/viewvc/llvm-project?rev=195079&view=rev.

For the comments, I'll keep on fixing them.

Thanks,
-Hao

From: cfe-commits-bounces at cs.uiuc.edu [mailto:cfe-commits-bounces at cs.uiuc.edu] On Behalf Of Jiangning Liu
Sent: Tuesday, November 19, 2013 10:14 AM
To: haoliuts at gmail.com; cfe-commits at cs.uiuc.edu; llvm-commits at cs.uiuc.edu for LLVM
Subject: Re: [PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post



2013/11/19 Jiangning Liu <liujiangning1 at gmail.com<mailto:liujiangning1 at gmail.com>>

  Hi Hao,

  Overall LGTM. For those two comments I gave I think you can do a refactoring work later on after committing this one.

  Since LLVM 3.4 branch is going to be created in an hour, and this patch is the only big feature we are missing for AArch64 Neon, I think you should go ahead to get it committed ASAP.

  Thanks,
  -Jiangning


================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1271
@@ -1049,1 +1270,3 @@
   }
+  case AArch64ISD::NEON_LD2DUP: {
+    static const uint16_t Opcodes[] = { AArch64::LD2R_8B,  AArch64::LD2R_4H,
----------------
This piece of code logic can be combined together with line 815, because they are quite related.  It would be better to centralize the relevant logic.

================
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1533
@@ -1212,1 +1532,3 @@
     }
+    case Intrinsic::arm_neon_vld2lane: {
+      static const uint16_t Opcodes[] = { AArch64::LD2LN_B, AArch64::LD2LN_H,
----------------
The same comments as line 1271.


http://llvm-reviews.chandlerc.com/D2211



--
Thanks,
-Jiangning

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