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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hi Jiangning,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Committed in r195078
</span><a href="http://llvm.org/viewvc/llvm-project?rev=195078&view=rev">http://llvm.org/viewvc/llvm-project?rev=195078&view=rev</a><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">and r195079
</span><a href="http://llvm.org/viewvc/llvm-project?rev=195079&view=rev">http://llvm.org/viewvc/llvm-project?rev=195079&view=rev</a><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">For the comments, I’ll keep on fixing them.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">-Hao<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> cfe-commits-bounces@cs.uiuc.edu [mailto:cfe-commits-bounces@cs.uiuc.edu]
<b>On Behalf Of </b>Jiangning Liu<br>
<b>Sent:</b> Tuesday, November 19, 2013 10:14 AM<br>
<b>To:</b> haoliuts@gmail.com; cfe-commits@cs.uiuc.edu; llvm-commits@cs.uiuc.edu for LLVM<br>
<b>Subject:</b> Re: [PATCH] Implement aarch64 neon instruction class SIMD lsone and lsone-post<o:p></o:p></span></p>
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<p class="MsoNormal">2013/11/19 Jiangning Liu <<a href="mailto:liujiangning1@gmail.com" target="_blank">liujiangning1@gmail.com</a>><o:p></o:p></p>
<p class="MsoNormal"><br>
Hi Hao,<br>
<br>
Overall LGTM. For those two comments I gave I think you can do a refactoring work later on after committing this one.<br>
<br>
Since LLVM 3.4 branch is going to be created in an hour, and this patch is the only big feature we are missing for AArch64 Neon, I think you should go ahead to get it committed ASAP.<br>
<br>
Thanks,<br>
-Jiangning<br>
<br>
<br>
================<br>
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1271<br>
@@ -1049,1 +1270,3 @@<br>
}<br>
+ case AArch64ISD::NEON_LD2DUP: {<br>
+ static const uint16_t Opcodes[] = { AArch64::LD2R_8B, AArch64::LD2R_4H,<br>
----------------<br>
This piece of code logic can be combined together with line 815, because they are quite related. It would be better to centralize the relevant logic.<br>
<br>
================<br>
Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1533<br>
@@ -1212,1 +1532,3 @@<br>
}<br>
+ case Intrinsic::arm_neon_vld2lane: {<br>
+ static const uint16_t Opcodes[] = { AArch64::LD2LN_B, AArch64::LD2LN_H,<br>
----------------<br>
The same comments as line 1271.<br>
<br>
<br>
<a href="http://llvm-reviews.chandlerc.com/D2211" target="_blank">http://llvm-reviews.chandlerc.com/D2211</a><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">Thanks,</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-family:"Courier New"">-Jiangning</span><o:p></o:p></p>
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