[PATCH]AArch64 Neon Post-index Load/Store multiple N-element instructions.

[Hao Liu]

Hi Tim,

 

This llvm patch implements post-index load/store multiple N-element
instructions. As these instructions share the same ACLE functions with
normal load/store multiple N-element instructions (my last patch), there is
no patch for Clang.

 

The implementation of these instructions are according to ARM backend, which
replace normal load/store nodes in ISelLowing with post-index  nodes. 

There is a little difference with fixed offset in ARM backend. If the
increment is an immediate and equal to the length of the vector list, the
instruction is like:

           ld1, {v0.8b, v1,8b}, [x0], #16

The '#16' is similar to '!' of load/store post instructions in ARM backend.

 

The patch is also added to link: http://llvm-reviews.chandlerc.com/D2091.

Please review it.

 

Thanks,

-Hao   
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