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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Hi Tim,<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This llvm patch implements post-index load/store multiple N-element instructions. As these instructions share the same ACLE functions with normal load/store multiple N-element instructions (my last patch), there is no patch for Clang.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The implementation of these instructions are according to ARM backend, which replace normal load/store nodes in ISelLowing with post-index nodes. <o:p></o:p></p><p class=MsoNormal>There is a little difference with fixed offset in ARM backend. If the increment is an immediate and equal to the length of the vector list, the instruction is like:<o:p></o:p></p><p class=MsoNormal> ld1, {v0.8b, v1,8b}, [x0], #16<o:p></o:p></p><p class=MsoNormal>The ‘#16’ is similar to ‘!’ of load/store post instructions in ARM backend.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>The patch is also added to link: http://llvm-reviews.chandlerc.com/D2091.<o:p></o:p></p><p class=MsoNormal>Please review it.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Thanks,<o:p></o:p></p><p class=MsoNormal>-Hao <o:p></o:p></p></div></body></html>