[cfe-commits] [llvm-commits] The AArch64 LLVM (& Clang) target

[Jakob Stoklund Olesen]

On Jan 7, 2013, at 4:57 AM, Tim Northover <Tim.Northover at arm.com> wrote:

> Hi all,
> 
> I now finally have permission to start upstreaming the long-delayed backend
> for
> ARM's new 64-bit architecture, AArch64.

Neat!

This isn't a full review, just some thing I noticed when reading your patch.

The changes to files outside lib/Target/AArch64 are probably best dealt with as separate patches.

+++ b/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+// This file contains a pass that expands pseudo instructions into target
+// instructions to allow proper scheduling, if-conversion, and other late
+// optimizations. This pass should be run after register allocation but before
+// the post-regalloc scheduling pass.

This pass isn't necessary. Just override TII::expandPostRAPseudo().

+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
+// Registers are identified with 5-bit ID numbers.
+class AArch64Reg<bits<5> num, string n> : Register<n> {
+  field bits<5> Num;
+  let Namespace = "AArch64";
+}

You should go ahead and stick the register number in the HWEncoding field, see how that works in the ARMRegisterInfo.td file. This makes the encoding number available from MCRegisterInfo::getEncodingValue().

+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+// FIXME: Better way. Surely TableGen can generate these LLVM <-> Architectural
+// mappings. See also MCTargetDesc/AArch64BaseInfo.h.
+static const unsigned GPR64DecoderTable[] = {
+  AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
+  AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7,
+  AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11,
+  AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15,
+  AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
+  AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23,
+  AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27,
+  AArch64::X28, AArch64::X29, AArch64::X30, AArch64::XZR
+};

It certainly can, and it does. Use MCRegisterInfo::getEncodingValue() and MCRegisterClass::getRegister().

+++ b/lib/Target/AArch64/MCTargetDesc/AArch64BaseInfo.h
+/// getAArch64RegisterNumbering - Given the enum value for some register, e.g.
+/// AArch64::LR, return the number that it corresponds to (e.g. 14).
+inline static unsigned getAArch64RegisterNumbering(unsigned Reg) {

Use MCRegisterInfo::getEncodingValue().

/jakob