[cfe-commits] [llvm-commits] [llvm] r139986 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sse-minmax.ll test/CodeGen/X86/sse41-blend.ll
Craig Topper
craig.topper at gmail.com
Mon Sep 19 09:13:23 PDT 2011
Any reason to not support f32 and v4f32 if only SSE1 is supported? Also
v8f32 and v4f64 could be added for 256-bit AVX.
On Sat, Sep 17, 2011 at 9:49 AM, Duncan Sands <baldrick at free.fr> wrote:
> Author: baldrick
> Date: Sat Sep 17 11:49:39 2011
> New Revision: 139986
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139986&view=rev
> Log:
> Synthesize x86 max/min instructions also for vectors (i.e. produce
> maxps and maxpd). This broke the sse41-blend.ll testcase by causing
> maxpd to be produced rather than a cmp+blend pair, which is the reason
> I tweaked it. Gives a small speedup on doduc with dragonegg when the
> GCC vectorizer is used.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/test/CodeGen/X86/sse-minmax.ll
> llvm/trunk/test/CodeGen/X86/sse41-blend.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139986&r1=139985&r2=139986&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Sep 17 11:49:39 2011
> @@ -1129,6 +1129,7 @@
> setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
> setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
> setTargetDAGCombine(ISD::BUILD_VECTOR);
> + setTargetDAGCombine(ISD::VSELECT);
> setTargetDAGCombine(ISD::SELECT);
> setTargetDAGCombine(ISD::SHL);
> setTargetDAGCombine(ISD::SRA);
> @@ -12551,7 +12552,8 @@
> return SDValue();
> }
>
> -/// PerformSELECTCombine - Do target-specific dag combines on SELECT
> nodes.
> +/// PerformSELECTCombine - Do target-specific dag combines on SELECT and
> VSELECT
> +/// nodes.
> static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
> const X86Subtarget *Subtarget) {
> DebugLoc DL = N->getDebugLoc();
> @@ -12564,9 +12566,9 @@
> // instructions match the semantics of the common C idiom x<y?x:y but not
> // x<=y?x:y, because of how they handle negative zero (which can be
> // ignored in unsafe-math mode).
> - if (Subtarget->hasXMMInt() &&
> - (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64)
> &&
> - Cond.getOpcode() == ISD::SETCC) {
> + if (Subtarget->hasXMMInt() && Cond.getOpcode() == ISD::SETCC &&
> + (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64 ||
> + LHS.getValueType() == MVT::v4f32 || LHS.getValueType() ==
> MVT::v2f64)) {
> ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
>
> unsigned Opcode = 0;
> @@ -13871,6 +13873,7 @@
> default: break;
> case ISD::EXTRACT_VECTOR_ELT:
> return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
> + case ISD::VSELECT:
> case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
> case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
> case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
>
> Modified: llvm/trunk/test/CodeGen/X86/sse-minmax.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=139986&r1=139985&r2=139986&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse-minmax.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse-minmax.ll Sat Sep 17 11:49:39 2011
> @@ -1,6 +1,6 @@
> -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs |
> FileCheck %s
> -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs
> -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck
> -check-prefix=UNSAFE %s
> -; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs
> -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
> +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs
> -promote-elements | FileCheck %s
> +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs
> -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck
> -check-prefix=UNSAFE %s
> +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs
> -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE
> %s
>
> ; Some of these patterns can be matched as SSE min or max. Some of
> ; then can be matched provided that the operands are swapped.
> @@ -933,3 +933,35 @@
> %x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double>
> [#uses=1]
> ret double %x_addr.0
> }
> +
> +; UNSAFE: maxpd:
> +; UNSAFE: maxpd
> +define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
> + %max_is_x = fcmp oge <2 x double> %x, %y
> + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %max
> +}
> +
> +; UNSAFE: minpd:
> +; UNSAFE: minpd
> +define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
> + %min_is_x = fcmp ole <2 x double> %x, %y
> + %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %min
> +}
> +
> +; UNSAFE: maxps:
> +; UNSAFE: maxps
> +define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
> + %max_is_x = fcmp oge <4 x float> %x, %y
> + %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y
> + ret <4 x float> %max
> +}
> +
> +; UNSAFE: minps:
> +; UNSAFE: minps
> +define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
> + %min_is_x = fcmp ole <4 x float> %x, %y
> + %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y
> + ret <4 x float> %min
> +}
>
> Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139986&r1=139985&r2=139986&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Sat Sep 17 11:49:39 2011
> @@ -73,10 +73,10 @@
>
> ; CHECK: B
> define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
> - ; CHECK: cmpltpd
> + ; CHECK: cmpnlepd
> ; CHECK: blendvpd
> - %max_is_x = fcmp ogt <2 x double> %x, %y
> - %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
> - ret <2 x double> %max
> + %min_is_x = fcmp ult <2 x double> %x, %y
> + %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
> + ret <2 x double> %min
> }
>
>
>
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>
--
~Craig
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