Any reason to not support f32 and v4f32 if only SSE1 is supported? Also v8f32 and v4f64 could be added for 256-bit AVX.<br><br><div class="gmail_quote">On Sat, Sep 17, 2011 at 9:49 AM, Duncan Sands <span dir="ltr"><<a href="mailto:baldrick@free.fr">baldrick@free.fr</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Author: baldrick<br>
Date: Sat Sep 17 11:49:39 2011<br>
New Revision: 139986<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=139986&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=139986&view=rev</a><br>
Log:<br>
Synthesize x86 max/min instructions also for vectors (i.e. produce<br>
maxps and maxpd). This broke the sse41-blend.ll testcase by causing<br>
maxpd to be produced rather than a cmp+blend pair, which is the reason<br>
I tweaked it. Gives a small speedup on doduc with dragonegg when the<br>
GCC vectorizer is used.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/sse-minmax.ll<br>
llvm/trunk/test/CodeGen/X86/sse41-blend.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139986&r1=139985&r2=139986&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=139986&r1=139985&r2=139986&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Sep 17 11:49:39 2011<br>
@@ -1129,6 +1129,7 @@<br>
setTargetDAGCombine(ISD::VECTOR_SHUFFLE);<br>
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);<br>
setTargetDAGCombine(ISD::BUILD_VECTOR);<br>
+ setTargetDAGCombine(ISD::VSELECT);<br>
setTargetDAGCombine(ISD::SELECT);<br>
setTargetDAGCombine(ISD::SHL);<br>
setTargetDAGCombine(ISD::SRA);<br>
@@ -12551,7 +12552,8 @@<br>
return SDValue();<br>
}<br>
<br>
-/// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.<br>
+/// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT<br>
+/// nodes.<br>
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,<br>
const X86Subtarget *Subtarget) {<br>
DebugLoc DL = N->getDebugLoc();<br>
@@ -12564,9 +12566,9 @@<br>
// instructions match the semantics of the common C idiom x<y?x:y but not<br>
// x<=y?x:y, because of how they handle negative zero (which can be<br>
// ignored in unsafe-math mode).<br>
- if (Subtarget->hasXMMInt() &&<br>
- (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&<br>
- Cond.getOpcode() == ISD::SETCC) {<br>
+ if (Subtarget->hasXMMInt() && Cond.getOpcode() == ISD::SETCC &&<br>
+ (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64 ||<br>
+ LHS.getValueType() == MVT::v4f32 || LHS.getValueType() == MVT::v2f64)) {<br>
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();<br>
<br>
unsigned Opcode = 0;<br>
@@ -13871,6 +13873,7 @@<br>
default: break;<br>
case ISD::EXTRACT_VECTOR_ELT:<br>
return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);<br>
+ case ISD::VSELECT:<br>
case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);<br>
case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);<br>
case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse-minmax.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=139986&r1=139985&r2=139986&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=139986&r1=139985&r2=139986&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse-minmax.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse-minmax.ll Sat Sep 17 11:49:39 2011<br>
@@ -1,6 +1,6 @@<br>
-; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs | FileCheck %s<br>
-; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s<br>
-; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s<br>
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -promote-elements | FileCheck %s<br>
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=UNSAFE %s<br>
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math -promote-elements | FileCheck -check-prefix=FINITE %s<br>
<br>
; Some of these patterns can be matched as SSE min or max. Some of<br>
; then can be matched provided that the operands are swapped.<br>
@@ -933,3 +933,35 @@<br>
%x_addr.0 = select i1 %0, double 3.000000e+03, double %x ; <double> [#uses=1]<br>
ret double %x_addr.0<br>
}<br>
+<br>
+; UNSAFE: maxpd:<br>
+; UNSAFE: maxpd<br>
+define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {<br>
+ %max_is_x = fcmp oge <2 x double> %x, %y<br>
+ %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>
+ ret <2 x double> %max<br>
+}<br>
+<br>
+; UNSAFE: minpd:<br>
+; UNSAFE: minpd<br>
+define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {<br>
+ %min_is_x = fcmp ole <2 x double> %x, %y<br>
+ %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y<br>
+ ret <2 x double> %min<br>
+}<br>
+<br>
+; UNSAFE: maxps:<br>
+; UNSAFE: maxps<br>
+define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {<br>
+ %max_is_x = fcmp oge <4 x float> %x, %y<br>
+ %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y<br>
+ ret <4 x float> %max<br>
+}<br>
+<br>
+; UNSAFE: minps:<br>
+; UNSAFE: minps<br>
+define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {<br>
+ %min_is_x = fcmp ole <4 x float> %x, %y<br>
+ %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y<br>
+ ret <4 x float> %min<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse41-blend.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139986&r1=139985&r2=139986&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-blend.ll?rev=139986&r1=139985&r2=139986&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse41-blend.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse41-blend.ll Sat Sep 17 11:49:39 2011<br>
@@ -73,10 +73,10 @@<br>
<br>
; CHECK: B<br>
define <2 x double> @B(<2 x double> %x, <2 x double> %y) {<br>
- ; CHECK: cmpltpd<br>
+ ; CHECK: cmpnlepd<br>
; CHECK: blendvpd<br>
- %max_is_x = fcmp ogt <2 x double> %x, %y<br>
- %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y<br>
- ret <2 x double> %max<br>
+ %min_is_x = fcmp ult <2 x double> %x, %y<br>
+ %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y<br>
+ ret <2 x double> %min<br>
}<br>
<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>