[all-commits] [llvm/llvm-project] d9e8ad: [Hexagon] Use MCRegisterClass::hasSubClassEq in He...
Zach Goldthorpe via All-commits
all-commits at lists.llvm.org
Fri Sep 25 08:17:14 PDT 2026
Branch: refs/heads/users/zGoldthorpe/wide-copies/precommit
Home: https://github.com/llvm/llvm-project
Commit: d9e8ad1dc8af2c478f9580e95b81f4cd54a9c6b7
https://github.com/llvm/llvm-project/commit/d9e8ad1dc8af2c478f9580e95b81f4cd54a9c6b7
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
Log Message:
-----------
[Hexagon] Use MCRegisterClass::hasSubClassEq in HexagonBitTracker. NFCI. (#226110)
This avoids depending on the exact names of synthesized register classes
(motivated by #225809 which will change some of these) and generally
feels more future-proof.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: fb6bc7fd73b3881b50453a5ffb52e5c00ae590f1
https://github.com/llvm/llvm-project/commit/fb6bc7fd73b3881b50453a5ffb52e5c00ae590f1
Author: Florian Mayer <fmayer at google.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M openmp/runtime/src/kmp_affinity.cpp
M openmp/runtime/src/kmp_affinity.h
R openmp/runtime/test/affinity/no_leak_with_disabled.c
Log Message:
-----------
Revert "[clang] [OpenMP] Memory leaks in OpenMP when affinity is disabled" (#226292)
Reverts llvm/llvm-project#225441
Commit: f26431d1e224f1e704fc167c2f509e4221e04220
https://github.com/llvm/llvm-project/commit/f26431d1e224f1e704fc167c2f509e4221e04220
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/test/API/macosx/expedited-recent-reads/TestExpeditedRecentReads.py
Log Message:
-----------
[lldb][test] Strip the MTE tag in TestExpeditedRecentReads (#226272)
When the inferior runs with MTE enabled, both heap cases in
`TestExpeditedRecentReads.py` fail at their first stop:
```
AssertionError: [] == [] : the first stop should read the heap buffer from the stub; reads: [0x104da8a00,0x104da8c00)
AssertionError: [] == [] : the first stop should read the heap buffer from the stub; reads: [0x1047acb30,0x1047acb38), [0x1047acb30,0x1047acb38), ...
```
lldb did read the heap buffer. `calloc` returns a pointer with an MTE
tag in its top byte, and lldb strips the tag before it reads memory:
```
(lldb) breakpoint set -p "break here" -f main.c
(lldb) process launch --memory-tagging
...
(lldb) frame variable heap
(Payload *) heap = 0x0b000001005b0b30
(lldb) script v = lldb.frame.FindVariable("heap"); print("GetValueAsUnsigned: 0x%x" % v.GetValueAsUnsigned(0)); print("GetValueAsAddress: 0x%x" % v.GetValueAsAddress())
GetValueAsUnsigned: 0xb000001005b0b30
GetValueAsAddress: 0x1005b0b30
```
Reading `heap->values[0]` then sends `x1005b0a00,200`, which reads the
untagged address. `heap_range` takes the address from
`GetValueAsUnsigned`, which keeps the tag, so `covering` never matches
a read. Use `GetValueAsAddress`, which returns the address with the
non-addressable bits cleared.
Assisted-by: claude
Commit: d01d1da97442654ca837893d46c4b50463473687
https://github.com/llvm/llvm-project/commit/d01d1da97442654ca837893d46c4b50463473687
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/test/API/macosx/expedited-stack-memory/main.c
Log Message:
-----------
[lldb][test] Run TestExpeditedStackMemory's call chain on a new thread (#226248)
`test_memory_reads_when_examining_all_frames_locals` fails on some
machine,
```
AssertionError: 0 not greater than 0 : expected stack memory reads while examining deeper frames' stack-resident locals.
memory reads while examining locals: stack=0 heap=1 other=1 (total=2)
```
In the packet log of one run, lldb stops at dyld's `lldb_image_notifier`
before `main` runs, and reads image info array is on the main thread's
stack,
and lldb reads one cache line (512 bytes) in one go.
Due to the new feature #223417, debugserver keeps this range as a recent
read and sends it again at later stops. At the breakpoint in `func_e`,
`jThreadsInfo` also sends the recent reads, which cover the call chain's
stack by accident, so lldb reads every local on every frame from its
cache
and the walk sends no stack read. That is why test failed.
Run the call chain on a new thread. No stop before the breakpoint reads
that thread's stack, so a recent read cannot cover the frames under
test.
Assisted-by: claude
Commit: 51fe9ce8248d783bb6b3b96fe883dd8cd05642ad
https://github.com/llvm/llvm-project/commit/51fe9ce8248d783bb6b3b96fe883dd8cd05642ad
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86FastISel.cpp
A llvm/test/CodeGen/X86/fast-isel-call-frame-dead-eflags.ll
Log Message:
-----------
X86: Mark the EFLAGS def of the FastISel call frame pseudos dead (#226281)
ADJCALLSTACKDOWN/UP are declared to clobber EFLAGS because they may
expand to a sub/add, but nothing reads the result. SelectionDAG's InstrEmitter
marks the def dead.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 5b47a7c81c5518f5c603a9203a23beed869d00f5
https://github.com/llvm/llvm-project/commit/5b47a7c81c5518f5c603a9203a23beed869d00f5
Author: aokblast <aokblast at FreeBSD.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
A llvm/test/Transforms/SCCP/fastmath-flags.ll
Log Message:
-----------
[SCCP] Call correct simplifyBinOp in FP operation (#225992)
This simplify FPOps with correct FMF, which covers non-inlined functions
that can not be simplified by InstComb pass.
Commit: f33b28a6979d6db40096da872befbf923357c322
https://github.com/llvm/llvm-project/commit/f33b28a6979d6db40096da872befbf923357c322
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
M lldb/source/Expression/UserExpression.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Utility/Policy.cpp
M lldb/unittests/Utility/PolicyTest.cpp
Log Message:
-----------
[lldb] Consult Policy for expression evaluation capabilities (#225312)
`can_evaluate_expressions`, `can_run_all_threads` and
`can_try_all_threads` have been unused since 3fe311f215d0 added them:
nothing outside `Policy.h` and its unit test ever read them.
Two of them already had a hand-rolled equivalent, though.
`Target::EvaluateExpression` forces single-threaded execution while a
frame provider is active, which is what the two thread capabilities
describe. That check predates them by six weeks (e1cd55879b5f) and the
adoption patch never came back for it. Living in `Target` also means it
only sees expressions that go through `Target`, not the ones coming from
`FunctionCaller` or `IRInterpreter`.
This patch changes that to consult the capabilities where the decision
is actually made: `UserExpression::Evaluate` for
`can_evaluate_expressions`, and `RunThreadPlan` for the other two. The
Target check goes away.
`RunThreadPlan` refuses rather than rewrites. Clearing stop-others asks
for the other threads, and since that option defaults to true, clearing
it is deliberate, so it errors instead of being silently turned back on.
Asking for the all-threads retry is refused the same way. The retry is
still switched off quietly when the caller never asked for it, since
that option defaults to on and so says nothing about intent.
It also checks the thread capabilities in `CreateScriptedExtensionCall`
rather than somewhere frame-provider specific. Not altering the state
you were asked to describe applies to any extension the debugger calls
into, so this increases the scope of the check it replaces: synthetic
children, OS plugin thread lists and scripted thread plans are now
covered too.
Since scripted commands set `UserCanRunDirectly` to true, the
`ScriptedExtensionCall` policy never gets pushed, so these expression
evaluation capabilities are kept and that is the behavior we want: the
user invoked the command directly, so there is no debugger operation
already in flight whose state it could alter.
rdar://176223894
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 590116564fd9045db6a950102dd772e864a6a9fc
https://github.com/llvm/llvm-project/commit/590116564fd9045db6a950102dd772e864a6a9fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/tools/llc/lib/llcdriver.cpp
Log Message:
-----------
llc: Compute the DataLayout from the triple and ABI (#224576)
This is the minimum change to avoid createDataLayout. Future work
will be needed here to really drop use of the ABIName field.
Commit: 4bd5979264ba739f8cb266b90c40e519eb7f3008
https://github.com/llvm/llvm-project/commit/4bd5979264ba739f8cb266b90c40e519eb7f3008
Author: Joe Nash <joseph.nash at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
A llvm/test/CodeGen/AMDGPU/vopd3-f64-opy-last-vgpr-gfx1250.mir
Log Message:
-----------
[AMDGPU] Work around gfx1250 VOPD3 FP64 OPY hazard (#224741)
In a VOPD3 instruction whose OPX is a 64-bit operation, an OPY VGPR
source operand reads back the wrong value when it is the last VGPR the
wave owns.
A wave always owns a whole number of VGPR allocation granules, 16
registers each on gfx1250, so the last VGPR it owns is always the one
just below a granule boundary. Reject a pair whose OPY reads such a
register in checkVOPDRegConstraints, leaving the two components as
separate instructions.
VOPD is only an optimization, so losing a pairing is always safe.
The workaround is gated on a new vopd3-f64-opy-src-hazard subtarget
feature, enabled for gfx1250, gfx1251, gfx1250-strict.
Assisted-by: Claude Code:claude-opus-5
Commit: fed2b1df79fc9e0668093c8e91aaf9b85ce1d5da
https://github.com/llvm/llvm-project/commit/fed2b1df79fc9e0668093c8e91aaf9b85ce1d5da
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/test/CodeGen/RISCV/machine-sink-jumptable-edge-split.ll
Log Message:
-----------
[RISCV] Add RUN lines for other code-models and PIC to machine-sink-jumptable-edge-split.ll. NFC (#226235)
Commit: b4fafec40e20f1de3b672f5354529063ef8acc74
https://github.com/llvm/llvm-project/commit/b4fafec40e20f1de3b672f5354529063ef8acc74
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/mvbits-unsigned.f90
Log Message:
-----------
[flang] Convert unsigned MVBITS TO values before arith ops (#226189)
Load TO with its memory type and insert fir.convert to a signless
integer instead of a typed fir.load whose result type does not match the
referent. Mem2Reg otherwise forwards the stored unsigned value into
arith.andi, which only accepts signless integers.
Previously, MVBITS of UNSIGNED lowered TO as:
```
%to = fir.load %addr : !fir.ref<ui8> // result type i8
%and = arith.andi %mask, %to : i8
```
Generic form:
```
%to = "fir.load"(%addr) : (!fir.ref<ui8>) -> i8
```
Commit: d051060325e27aba3536419925f985321e441db9
https://github.com/llvm/llvm-project/commit/d051060325e27aba3536419925f985321e441db9
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/CodeGenCXX/GH176161.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
Log Message:
-----------
[Clang] Re-analyze parenthesized aggregate mem-initializers on instantiation (#224918)
Fixes #176161
Fixes #189005
Fixes #213284
Since #138518, template instantiation keeps a parenthesized aggregate
initialization as a `CXXParenListInitExpr`, but its elements have
already been reverted to their written form (a braced list stays a
braced list, an implicit cast is stripped), so whoever consumes the node
has to redo the initialization from them. Variable initializers,
new-expressions and functional casts do that. `BuildMemberInitializer`
didn't: it took the whole node as one argument, guaranteed elision
accepted it as-is, and the constructor ended up with a member
initializer that was never analyzed. Depending on the shape that's the
`EmitAggExpr` assertion (#176161, #189005), a `0` stored as 32 bits into
a 64-bit field (#213284), a rejected valid array member like `arr(1,
2)`, or a union member silently left uninitialized. Clang 20 handled all
of these. The lambda and local class in #176161 are incidental; a plain
class template reproduces it.
`BuildMemberInitializer` now treats a `CXXParenListInitExpr` the way it
treats a `ParenListExpr` and performs the initialization from the
user-specified elements. Using only those elements (not the trailing
default-member-initializer and value-initialization ones Sema appends)
means they get rebuilt for the instantiated class rather than fed back
in as arguments. This mirrors what #141342 did for variable initializers
and #142988 for new-expressions, and supersedes #213565.
Commit: 482bb48e9dd8c2b69bec4923d94252f88a7bff5e
https://github.com/llvm/llvm-project/commit/482bb48e9dd8c2b69bec4923d94252f88a7bff5e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Log Message:
-----------
[SCEV] Handle PtrToAddrExpr in SCEVLoopGuardRewriter. (#226228)
Adding support for PtrToAddr to loop guard rewriting was missed during
the initial bring-up.
Fixes https://github.com/llvm/llvm-project/issues/225918.
PR: https://github.com/llvm/llvm-project/pull/226228
Commit: ef8d9d19fb232076b7a2070860666a65a2cf563e
https://github.com/llvm/llvm-project/commit/ef8d9d19fb232076b7a2070860666a65a2cf563e
Author: oltolm <oleg.tolmatcev at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M compiler-rt/lib/asan/asan_globals_win.cpp
M compiler-rt/lib/asan/asan_win.cpp
M compiler-rt/lib/asan/asan_win_common_runtime_thunk.h
M compiler-rt/lib/sanitizer_common/sanitizer_win_defs.h
M compiler-rt/lib/sanitizer_common/sanitizer_win_thunk_interception.cpp
Log Message:
-----------
[compiler-rt] Retain sanitizer callbacks with MinGW GCC (#222711)
MSVC and clang-cl use /include directives emitted by WIN_FORCE_LINK. GNU
tools need an ordinary used relocation instead. Keep the sanitizer
initialization callbacks and ASan DSO registration object reachable when
linking with MinGW GCC.
---------
Co-authored-by: Hannes Domani <ssbssa at yahoo.de>
Commit: 16d88a5e65b141b4ecf7a237c6104e1425a335d9
https://github.com/llvm/llvm-project/commit/16d88a5e65b141b4ecf7a237c6104e1425a335d9
Author: oltolm <oleg.tolmatcev at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M compiler-rt/lib/asan/asan_win.cpp
Log Message:
-----------
[compiler-rt][asan] Use native TLS for TSD on Windows (#222705)
GCC 16 supports native Windows TLS. Use compiler-rt's THREADLOCAL
abstraction for fake_tsd on all compilers instead of spelling the
MSVC-specific storage-class syntax directly. GCC configurations using
emulated TLS remain unsupported.
Co-authored-by: Hannes Domani <ssbssa at yahoo.de>
Commit: 2b8362fe2e2a04c8905d445fb5e7407dda32e742
https://github.com/llvm/llvm-project/commit/2b8362fe2e2a04c8905d445fb5e7407dda32e742
Author: Tom Honermann <tom.honermann at intel.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M libsycl/src/CMakeLists.txt
A libsycl/test/basic/linux-rpath.test
M libsycl/test/lit.cfg.py
Log Message:
-----------
[libsycl] Add $ORIGIN to RPATH for libLLVMSYCL (#224885)
Previously, libLLVMSYCL was built and installed without $ORIGIN set in
RPATH on ELF systems. This resulted in load failures due to failure to
find libLLVMOffload when LD_LIBRARY_PATH was not set. This change adds
$ORIGIN to RPATH both when building libLLVMSYCL in a build tree, and
when installing libLLVMSYCL in an install tree.
Commit: 9c0f5509f959b0d44e2f2395bb5ef8e89eacac0b
https://github.com/llvm/llvm-project/commit/9c0f5509f959b0d44e2f2395bb5ef8e89eacac0b
Author: Christian Kandeler <christian.kandeler at qt.io>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/lib/Sema/HeuristicResolver.cpp
M clang/unittests/Sema/HeuristicResolverTest.cpp
Log Message:
-----------
[clang][HeuristicResolver] Resolve more dependent member accesses (#223667)
`HeuristicResolver` already falls back to a template parameter's default
argument when there is nothing else it can do with the parameter, but it
only did so when it met the parameter directly. Two common ways of
arriving at one were missed, both of which occur in `std::vector`:
- through a dependent name — libstdc++ has `typedef _Alloc
allocator_type;`, so `std::vector<T>::allocator_type` resolves to a bare
template parameter;
- through the sugar of the member typedef itself, e.g. when it is the
declared return type of a member function.
Neither can be done on a canonicalized type: a canonical
`TemplateTypeParmType` does not retain its `TemplateTypeParmDecl` (see
`ASTContext::getTemplateTypeParmType()`), so there is no default
argument left to consult. The typedef's underlying type as written is
consulted instead.
A separate gap shows up on the same example. A member re-exported from a
dependent base class by a using declaration, such as libstdc++'s `using
_Base::get_allocator;`, is found as an `UnresolvedUsingValueDecl`, which
has no function type of its own, so `resolveTypeOfCallExpr()` could not
determine the type of a call to it. Such a declaration is now resolved
to what it names, using the existing `resolveUsingValueDecl()`.
Together these make code completion work for, for example:
```c++
template <class T> void f(std::vector<T> &v) {
typename std::vector<T>::allocator_type al = v.get_allocator();
al. // now offers std::allocator's members
}
```
Tests are also added for cases the heuristic does not get right, so that
they are recorded and will be noticed if that ever changes: a parameter
whose default argument is not the one we end up looking at, because
looking a name up in a base class's primary template discards the
arguments the derived class passes to it; and an explicitly provided
template argument being ignored in favour of the default. Tests
asserting that a name does not resolve now state whether that is the
desired behaviour or a limitation worth lifting.
Commit: 2cd5243774ef4d825d7118b39ec1085d39a7bbe7
https://github.com/llvm/llvm-project/commit/2cd5243774ef4d825d7118b39ec1085d39a7bbe7
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/test/CodeGen/AArch64/constant-pool-partition.ll
M llvm/test/CodeGen/AArch64/jump-table-partition.ll
M llvm/test/CodeGen/X86/global-variable-partition.ll
Log Message:
-----------
[StaticDataLayout] Add option to control the emission of .hot suffix (#226239)
We have not thoroughly studied the impact of separating out lukewarm/hot
data into separate sections. This option gives us a way to consolidate
the sections and enables easy experimentation.
Co-Authored-By: Mingming Liu <mingmingl at google.com>
Commit: 8bff8fbc71f43a1f721aa6403e0e66e913c05395
https://github.com/llvm/llvm-project/commit/8bff8fbc71f43a1f721aa6403e0e66e913c05395
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll
M llvm/test/Transforms/PGOProfile/data-access-profile.ll
Log Message:
-----------
[StaticDataLayout] Enable string literal partitioning by default (#225928)
We have started to roll this out internally, so enable it by default
upstream as well. This will enable seamless removal of the flag
internally with respect to our release process.
Commit: 0326d5ca1c402a0295c5115a51a1ba080f94a9c5
https://github.com/llvm/llvm-project/commit/0326d5ca1c402a0295c5115a51a1ba080f94a9c5
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[LV] Add more tests with low trip counts. (NFC) (#226298)
Add additional tests with low trip counts where TC == VF.
Commit: 92289bdbced90ccc9f63da0c7fdaa71879c70964
https://github.com/llvm/llvm-project/commit/92289bdbced90ccc9f63da0c7fdaa71879c70964
Author: Thomas Köppe <tkoeppe at google.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M openmp/runtime/src/kmp_affinity.cpp
M openmp/runtime/src/kmp_affinity.h
A openmp/runtime/test/affinity/no_leak_with_disabled.c
Log Message:
-----------
[Clang][OpenMP] Reapply "Memory leaks in OpenMP when affinity is disabled" (#226292) (#226294)
The previous version was applying a compiler flag to the smoke test
that would result in an unrunnable binary on non-ARM platforms. The
intention is for ASAN on ARM to run, and we get that by just not
specifying any flags and relying on the test system to include this
platform.
Commit: f9d25d67d4f7a5b9c37047306a700b234fd6c2c8
https://github.com/llvm/llvm-project/commit/f9d25d67d4f7a5b9c37047306a700b234fd6c2c8
Author: Minsoo Choo <minsoo at minsoo.io>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
Log Message:
-----------
[lldb][FreeBSD] Adopt file_t for closeFile() (#226290)
Fixes: ae82b85123a2271df24ceb28c09a2a0c467c16d5
Commit: 4010c1ac00e25464ecc7e20950cba84edd0e3880
https://github.com/llvm/llvm-project/commit/4010c1ac00e25464ecc7e20950cba84edd0e3880
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[MLIR] Reduce generated assembly printer compile time (NFC) (#225740)
Use fixed arrays for statically elided attributes and combine leading
spaces with literals. Move common operand printing out of generated call
sites and emit sliced operand getters to reduce optimizer work in large
printers.
For omp.target, optimized print IR drops from 3,893 to 2,667
instructions.
Assisted-by: Codex
Commit: a858e5ebb33c3988ac593cefe4593040029169b4
https://github.com/llvm/llvm-project/commit/a858e5ebb33c3988ac593cefe4593040029169b4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[LV] Add tests showing incorrect flags for sub inductions (NFC). (#226301)
Add tests showing incorrect NUW/NSW flags preserved on wide induction
where the induction step uses sub.
Tests for https://github.com/llvm/llvm-project/issues/224024.
Commit: 5e7f66672867f3ccf23baa6156d16ec4541de29b
https://github.com/llvm/llvm-project/commit/5e7f66672867f3ccf23baa6156d16ec4541de29b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Log Message:
-----------
[mlir][ODS] Share generated legacy property splitting (NFC) (#226085)
Route generated legacy builder attributes through an out-of-line helper
that partitions inherent and discardable attributes before converting
properties. This avoids compiling the same loop and error path for every
operation.
Assisted-by: Codex
Commit: 45ea3b957284d8940b109b6b6706f451e9719ef9
https://github.com/llvm/llvm-project/commit/45ea3b957284d8940b109b6b6706f451e9719ef9
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/builtins/InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
A clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
M clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat-unsupported-width.ll
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
Log Message:
-----------
[HLSL] Add float overload for `InterlockedExchange` (#222163)
This PR adds the float overload of `InterlockedExchange`, and the
`InterlockedExchangeFloat` method on `RWByteAddressBuffer` and
`RasterizerOrderedByteAddressBuffer`.
The HLSL interlocked builtins are declared with a variadic type in
`Builtins.td`, so Clang applies the default argument promotions to their
arguments. That promotion turns a `float` argument into a `double`
before Sema
sees it. The Sema check then rejects the call and names the type as
`'double'`
in the diagnostic, which does not match what the user wrote.
`CustomTypeChecking` suppresses that promotion, so the argument keeps
its
`float` type and the diagnostic names it correctly.
Only the builtins that can see a float argument need the attribute. This
PR
sets it on `__builtin_hlsl_interlocked_exchange` alone. The later float
builtins in this stack set it as they are added. The integer-only
builtins do
not set it, because they never see a float and the promotion cannot
affect
them.
Fixes: https://github.com/llvm/llvm-project/issues/99129
Assisted by: Github Copilot
Commit: 3a4d4104528d44e1bae74464f8a104d7ee86a7ac
https://github.com/llvm/llvm-project/commit/3a4d4104528d44e1bae74464f8a104d7ee86a7ac
Author: Ivan R. Ivanov <iivanov at nvidia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/include/device.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libompaccsupport/PluginManager.cpp
M offload/libompaccsupport/device.cpp
M offload/libomptarget/OffloadRTL.cpp
M offload/libomptarget/OpenMP/OMPT/Callback.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[offload] Extract OMPT out of PluginInterface (#221726)
Some of the OMPT callbacks, namely the device lifetime and image related
ones, lived in the generic PluginInterface even though they are OpenMP
specific. This patch extracts them out to the PluginManager, and removes
some device ID tracking functionality which was only necessary for
OpenMP from PluginInterface. The OpenMP device ID mapping should live
only in libomptarget.
Commit: 16cbe80f1d294451026cc79d25754e98172d4d1f
https://github.com/llvm/llvm-project/commit/16cbe80f1d294451026cc79d25754e98172d4d1f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead when merging lane masks (#226282)
The scalar and/or/xor used to merge a lane mask with EXEC clobber SCC,
but nothing reads the result. Avoid depending on later dead flag inference.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 25ba11d9dd3053d82af538e8b2cd7d449dcc867c
https://github.com/llvm/llvm-project/commit/25ba11d9dd3053d82af538e8b2cd7d449dcc867c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/OpDefinition.h
Log Message:
-----------
[mlir] Constant-initialize registered operation hook tables (NFC) (#226320)
Make the generic operation hook accessors constexpr so registered
operation hook tables can be constant-initialized. Keep the table
declared static const to support non-constexpr downstream overrides.
In OpenMPDialect.cpp this removes 72 initialization guards and 10,368
bytes of object text, and saves about 0.56B compiler instructions.
Assisted-by: Codex
Commit: ec32f94a2d5f871624fce2e0c51c4902ee02ec15
https://github.com/llvm/llvm-project/commit/ec32f94a2d5f871624fce2e0c51c4902ee02ec15
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Add -show-jit-result option (#226149)
Add a -show-jit-result option that prints the int result of the JIT'd
main / entry function to stdout as:
JIT result: <return value>
This makes the result of the JIT'd main / entry function FileCheck-able,
and distinguishable from an llvm-jitlink failure.
This will be used in upcoming ORC runtime tests.
Since we don't currently run code under llvm-jitlink in LLVM regression
tests, this commit does not include an LLVM-side test.
Commit: 0d049f14804d436b12d81846de00c45516541f0b
https://github.com/llvm/llvm-project/commit/0d049f14804d436b12d81846de00c45516541f0b
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/lib/CodeGen/AllocationOrder.cpp
M llvm/lib/CodeGen/AllocationOrder.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/unittests/CodeGen/AllocationOrderTest.cpp
Log Message:
-----------
[RegAlloc] Add register allocation anti-hints infrastructure (#218071)
This PR adds a RA anti-hint mechanism. MachineRegisterInfo is extended
to track anti-hints
between vregs to try avoiding to be allocated on the same physical
register. AllocationOrder can
queries these and also allows the target reorder the allocation order
through the new
TargetRegisterInfo::applyRegAllocationAntiHints hook. The default
implementation moves
the anti-hinted registers to the end of the order, so they are only used
as a last option.
## Stack
PR **1/4**. Next: MIR serialization #218073.
Commit: 25485b3c4964ab704e7d4961b67ab2501fedbdbe
https://github.com/llvm/llvm-project/commit/25485b3c4964ab704e7d4961b67ab2501fedbdbe
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.h
M llvm/test/Transforms/SLPVectorizer/RISCV/wide-load-reduction.ll
Log Message:
-----------
[SLP] Use getRegUsageForType() rather than getNumberOfParts() when determining reduction width (#226277)
`getRegUsageForType()` is more appropriate for comparison to total
number of registers. `getNumberOfParts()` is legalization cost based,
but in this situation, we are looking to make sure we don't create
vectors that are widen than the register file can handle.
Commit: 9d90850fe6b01d877a7d7559a097fd4e785b4f5a
https://github.com/llvm/llvm-project/commit/9d90850fe6b01d877a7d7559a097fd4e785b4f5a
Author: Zachary Yedidia <zyedidia at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/docs/LFI.md
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
A llvm/lib/Target/X86/X86LFIRewritePass.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
A llvm/test/CodeGen/X86/lfi-align.ll
A llvm/test/MC/X86/LFI/control-flow-errors.s
A llvm/test/MC/X86/LFI/control-flow.s
Log Message:
-----------
[LFI][X86] Add control-flow rewrites (#210913)
This adds LFI rewrites for control-flow operations. All jumps and
calls are rewritten so that their target is both guaranteed to be within
the sandbox, and at an address that is a multiple of the bundle size.
When combined with bundling, this restricts control-flow to the sandbox
region.
With Intel MPK support, this can provide a complete sandbox. A future
patch will also introduce software-based memory sandboxing so that MPK
is not required for memory isolation.
Commit: 2428c10786f12f8e4e7bffa63b0393c137b031bb
https://github.com/llvm/llvm-project/commit/2428c10786f12f8e4e7bffa63b0393c137b031bb
Author: Greg Clayton <gclayton at fb.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
A llvm/test/tools/llvm-gsymutil/X86/macho-last-symbol-section-end.yaml
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
Log Message:
-----------
Improve llvm-gsymutil to set the end address correctly. (#225593)
When converting DWARF in llvm-gsymutil, if the last function info had no
size, it would set it to the end of the valid text ranges. This meant a
symbol could get a larger than necessary size in mach-o files. This
patch will set the address to the minimum of the last TextRanges or the
end of the section that contains the symbol.
Commit: 56e0b9a7d7acb82a2cc4499808277c388b1e4332
https://github.com/llvm/llvm-project/commit/56e0b9a7d7acb82a2cc4499808277c388b1e4332
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
Log Message:
-----------
[mlir][tosa] Use optnone for compliance initialization under HWAsan (#226310)
Similar to #223586, compiling the file is very slow when we enable
HWAsan internally. Mark the constructor with optnone under
LLVM_HWADDRESS_SANITIZER_BUILD to skip expensive optimization and
register allocation passes, bringing compilation time from 10+m to ~30s.
Commit: 73aa0db9662ca7e38337761076a622e8095011af
https://github.com/llvm/llvm-project/commit/73aa0db9662ca7e38337761076a622e8095011af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[RISCV][llvm-readobj] Treat RISC-V float ABI e_flags field as an enum (#226313)
EF_RISCV_FLOAT_ABI is a 2-bit field, not independent flag bits, so
printFlags needs to be told about the mask. Previously a quad-float ABI
object printed "single-float ABI, double-float ABI, quad-float ABI"
instead of just "quad-float ABI".
Co-Authored-By: Claude Sonnet 5 <noreply at anthropic.com>
Commit: eaddb12b0463d9baa048da856c21f50fa9bfc1cf
https://github.com/llvm/llvm-project/commit/eaddb12b0463d9baa048da856c21f50fa9bfc1cf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Make the getJumpTableIndex search more structured. NFC (#226266)
Instead of recursively searching through instructions with certain
opcodes, look for the specific patterns we use for jump tables.
I've added a few TODOs for Zilx and SHXADD_UW.
Commit: 2c6ac60714745ffc338e1b9664d10ec46212185b
https://github.com/llvm/llvm-project/commit/2c6ac60714745ffc338e1b9664d10ec46212185b
Author: Ziliang Zhang <zzl.coding at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Handle disjoint subsets in One-Shot Analysis (#224184)
Teach One-Shot Analysis to ignore RaW conflicts between provably
disjoint subset reads and writes. Trace aliasing reads back to subset
extraction ops to handle alias-only operations such as
tensor.extract_slice.
Add tensor and vector tests for disjoint, overlapping, and unknown
subsets.
Commit: 10e12674cb9c52611d1f3c3c4c92ce43b586b7fe
https://github.com/llvm/llvm-project/commit/10e12674cb9c52611d1f3c3c4c92ce43b586b7fe
Author: Ziliang Zhang <zzl.coding at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/one-shot-bufferize-analysis.mlir
M mlir/test/Dialect/Linalg/one-shot-bufferize.mlir
Log Message:
-----------
[mlir][bufferization] Support matching permutation maps in Linalg analysis (#226079)
Generalize `LinalgOpInterface::bufferizesToElementwiseAccess` to
recognize participating tensor operands with identical permutation
indexing maps, instead of requiring identity maps.
This enables in-place bufferization after loop interchange. Projected
and mismatching maps, reduction iterators, and sparse operands remain
conservatively rejected.
The tests cover the analysis decision as well as end-to-end
bufferization without an allocation or copy.
Commit: dd3534fd5af15575d0d8dea116740b2abb8f3328
https://github.com/llvm/llvm-project/commit/dd3534fd5af15575d0d8dea116740b2abb8f3328
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
R clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
Log Message:
-----------
[clang][DepScan] Disable relocation checks (#225563)
This internally broke an incremental build. Disable while it gets
investigated.
This is partial revert of cf8597bd3b87
resolves: rdar://188026923
Commit: 051daff864822f9edcb05acb8ccb30852753dfc5
https://github.com/llvm/llvm-project/commit/051daff864822f9edcb05acb8ccb30852753dfc5
Author: geoffreygaren <ggaren at apple.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M clang/docs/analyzer/checkers.md
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefSafetyModel.cpp
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
A clang/test/Analysis/Checkers/WebKit/unborrowed-lambda-captures.cpp
Log Message:
-----------
[WebKit Checkers] Add alpha.webkit.UnborrowedLambdaCapturesChecker (#226288)
Like alpha.webkit.UnborrowedLocalVarsChecker, but for lambda captures.
This checker is pretty restrictive because, unlike a refcounted object,
a lifetime-dependent pointer/reference/view cannot be captured in an
escaping closure at all. Still, we permit capturing in a NOESCAPE
closure.
Commit: 6e687f8dea8825c52fc6f31459dabb0ee0c1d4bd
https://github.com/llvm/llvm-project/commit/6e687f8dea8825c52fc6f31459dabb0ee0c1d4bd
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
A llvm/test/CodeGen/MIR/AMDGPU/register-allocation-antihints-mir-print-parse.mir
Log Message:
-----------
[MIR][AMDGPU] Serialize register allocation anti-hints (#218073)
This PR adds MIR print and parse support for the register allocation
anti-hints through
a per vreg anti-hints: [ .. ] field in the registers: section. The
printer only emits
the anti-hint registers only when the it is non-empty to keep existing
tests unchanged.
## Stack
PR **2/4**. Depends on #218071. Next: Apply Occupancy-Aware allocation
anti-hints #218074.
Commit: 7ee53ccefc851c05f3183b1d2cc5bf811cdb62df
https://github.com/llvm/llvm-project/commit/7ee53ccefc851c05f3183b1d2cc5bf811cdb62df
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
A clang/docs/HLSL/DynamicResources.md
M clang/docs/HLSL/HLSLDocs.md
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
M clang/lib/Headers/hlsl/hlsl_detail.h
A clang/lib/Headers/hlsl/hlsl_resources.h
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
A clang/test/AST/HLSL/DynamicResources-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
A clang/test/CodeGenHLSL/resources/dynamic-resources.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources-availability.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources.hlsl
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Log Message:
-----------
[HLSL] Add support for dynamic resources (#221103)
Adds support for dynamic resources, also known as bindless or directly
indexed resources. The design is described in
https://github.com/llvm/wg-hlsl/issues/204.
The change adds:
- The `ResourceDescriptorHeap` and `SamplerDescriptorHeap` global
symbols, which expose the Shader Model 6.6 descriptor heaps.
- Internal `hlsl::__detail::heap_resource_info` and
`hlsl::__detail::heap_sampler_info` types, which are produced by
indexing the corresponding descriptor heap. HLSL resource and sampler
types can be implicitly constructed from these values.
- Constructors that accept the corresponding internal heap info type for
all currently implemented resource classes.
- Clang builtins `__builtin_hlsl_resource_handlefromheap` and
`__builtin_hlsl_resource_counterhandlefromheap` for creating resource
and counter handles from descriptor heap indices.
- Sema validation and return-type handling for the new builtins.
For DXIL, the built-in function is lowered to
`llvm.dx.resource.handlefromheap`. For SPIR-V, the built-ins are lowered
to `llvm.spv.resource.handlefromheap` and
`llvm.spv.resource.counterhandlefromheap`.
Fixes #133831
Assisted by GPT 5.6 Sol and Claude Opus 4.8.
Commit: 35f073eb07f641713513fefb1ae4f4a5eb0bc604
https://github.com/llvm/llvm-project/commit/35f073eb07f641713513fefb1ae4f4a5eb0bc604
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
Log Message:
-----------
[AMDGPU] Fold a constant add/sub into the sudot4/sudot8 accumulator (#225322)
Fold a constant add into the accumulator operand of sudot4 and sudot8
when
clamping is disabled:
```
sudot(a, b, C1, false) + C2 -> sudot(a, b, C1 + C2, false)
```
Subtraction by a constant is canonicalized to addition of its negation.
Commit: 3243453c7b919c155a16e4e70e50d5f8417839d9
https://github.com/llvm/llvm-project/commit/3243453c7b919c155a16e4e70e50d5f8417839d9
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/test-at-commit
Log Message:
-----------
[libc++] Take the benchmark testing configuration from the test suite (#226267)
Previously, we'd use the testing configuration (the .cfg.in file) from
the checked out test suite for the PR benchmarking, but we'd use the one
from `main` for the historical benchmarking. Since the config file is
logically part of the test suite (just like the rest of the Lit setup),
it makes more sense to take it from the checked-out test suite version.
Commit: 4880e16f73dfc25762a857b9c08ad2bd5c14c8e0
https://github.com/llvm/llvm-project/commit/4880e16f73dfc25762a857b9c08ad2bd5c14c8e0
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
R llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-frame-flags.ll
A llvm/test/CodeGen/RISCV/sifive-interrupt-frame-pointer.ll
Log Message:
-----------
[RISCV] Support frame pointers in SiFive CLIC preemptible handlers (#221318)
This commit adds frame-pointer support for SiFive CLIC preemptible
handlers by using t0 to save mcause and mepc to dedicated stack slots in
both cases.
Commit: 8c237a2c9f979a7b8716ef1073d3a5a0558d1415
https://github.com/llvm/llvm-project/commit/8c237a2c9f979a7b8716ef1073d3a5a0558d1415
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx/build-at-commit/action.yml
Log Message:
-----------
[libc++] Run the PR benchmarking tooling from main (#226278)
Previously, we'd use the workflow file and machines.json from the main
branch, but the rest of the tools (e.g. build-at-commit) would be taken
from the PR head. This patch switches to using the tools from main and
only using the PR head's content for the actual code and benchmarks.
This should make it easier to evolve the tools and the workflow files
without breaking PR benchmarking for people who submit PRs from slightly
outdated bases.
Commit: f119c93418ebd6aa3a95b7346fe3f6c86fba57f7
https://github.com/llvm/llvm-project/commit/f119c93418ebd6aa3a95b7346fe3f6c86fba57f7
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Interpreter/CommandInterpreter.cpp
A lldb/test/Shell/ScriptInterpreter/Python/nested_command_selected_target.test
Log Message:
-----------
[lldb] Use the selected target when the override context is the dummy (#226332)
Commit: f91a3b1bcd7bb69634bc40da1f599daab2aea67c
https://github.com/llvm/llvm-project/commit/f91a3b1bcd7bb69634bc40da1f599daab2aea67c
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M bolt/test/X86/dwarf5-debug-names-skip-forward-decl.s
Log Message:
-----------
[BOLT,test] Add missing pipe in dwarf5-debug-names-skip-forward-decl.s (#226338)
With cl::Grouping, --check-prefix=POSTCHECK parses as -c -h..., so
llvm-dwarfdump prints --help and exits 0, and the checks never run.
Commit: b9123f788eb3e62c5cf18fd7d7b093dd3206b60d
https://github.com/llvm/llvm-project/commit/b9123f788eb3e62c5cf18fd7d7b093dd3206b60d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove cl::Grouping (#224958)
This feature emulates POSIX's grouped short options in a non-perfect
way. https://reviews.llvm.org/D61270 made every single-character
cl::option implicitly group, leading to weird error message for `opt
-foo=bar`: `opt: for the -o option: may not occur within a group!`
Every tool (primarily binutils-style tools) has since migrated to
OptTable,
with llvm-cov gcov the last (#224955).
Delete this feature, which would block TableGen based representation.
LLM-aided
Commit: e9c56af6e91289a9be5604c74309638d685999be
https://github.com/llvm/llvm-project/commit/e9c56af6e91289a9be5604c74309638d685999be
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
Log Message:
-----------
[GlobalISel] Fix segment size when narrowing G_INSERT (#226275)
When an inserted value starts inside a destination piece, bound the
overlap by the size of the inserted value. Including the offset from the
start of the piece can produce an extract wider than its source.
---------
Co-authored-by: Hongyu Chen <hongchen at nvidia.com>
Commit: 178caae5c39dbf9a03f52f9a3d7edc11d3b02405
https://github.com/llvm/llvm-project/commit/178caae5c39dbf9a03f52f9a3d7edc11d3b02405
Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.anti-hints.mir
Log Message:
-----------
[AMDGPU] Apply occupancy-aware register allocation anti-hints (#218074)
This PR overrides applyRegAllocationAntiHints in the SIRegisterInfo so
anti-hints
try to protect against occupancy regression. Changing of the allocation
order is
confined to the vgpr budget of the current occupancy. Reordering is
skipped when
the allocation is near the budget (80% of the target-occupancy vgpr
limit or 95%
of the current occupancy vgpr limit). Below this, the anti-hinted
registers are
moved behind the non-anti-hinted ones within the budget.
## Stack
PR **3/4**. Depends on #218073. Next: Add anti-hints in
GCNPreRAOptimizatioins #218075.
Commit: 007551bacb899a409218574908d96b0633d52018
https://github.com/llvm/llvm-project/commit/007551bacb899a409218574908d96b0633d52018
Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
Log Message:
-----------
[RISCV] Remove getInstSizeVerifyMode override (#226241)
Now that we generate the correct instruction sizes for the compressed
instructions we can remove this function override.
Commit: 3489ea3b567c719f497bfcf83348e27cfd79cdb7
https://github.com/llvm/llvm-project/commit/3489ea3b567c719f497bfcf83348e27cfd79cdb7
Author: Himadhith <hima130602 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/aix.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/newlib.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/openbsd.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/src/support/win32/locale_win32.cpp
Log Message:
-----------
[libcxx][locale] Refactor strtonum functions using __str_to_float_c_locale<FloatT> (#222081)
Replace the 3 separate functions `__strtof`, `__strtod` and `__strtold`
with a single template `__str_to_float_c_locale<FloatT>` across
locale_base_api and all platform support headers. Since
`__str_to_float_c_locale<FloatT>` now does not need `__get_c_locale`
argument we can directly call it instead of `__do_strtod`.
This removes `__setAndRestore` from `aix.h` entirely as `__locale_guard`
is now used directly in the template specialisations to switch locales.
`num.h` is updated to call `__locale::__str_to_float_c_locale<T>`
uniformly across the 3 separate `__do_strtod` specialisation calls.
Additionally,
- linux.h, bsd_like.h, newlib.h delegate to the platform's native
`strtof_l`/`strtod_l`/`strtold_l`.
- openbsd.h, no_locale/strtonum.h call bare `strtof`, `strtod` and
`strtold` (no locale needed).
- windows.h, locale_win32.cpp's MSVCRT path inlines the 3 functions and
the non-MSVCRT path exports explicit specialisations from the library.
- Changes `__locale_guard` to take `__locale_t` by value now by removing
`&`.
- Forward declared the `__get_c_locale()` function as it's being used
well before the include.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: 585df631037b5cf8d822b9d6de5abb74cf79d1f4
https://github.com/llvm/llvm-project/commit/585df631037b5cf8d822b9d6de5abb74cf79d1f4
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
A lldb/test/Shell/ObjectFile/wasm/data-segment-names.yaml
Log Message:
-----------
[lldb] Index Wasm data segment names by their entry's index (#226302)
ParseNames bounds-checked each data segment name entry's index but wrote
the name to the slot of the loop counter. A name subsection with more
entries than segments wrote past the end of the segment vector, and
entries listed out of order named the wrong segment.
rdar://186890690
Commit: 8e7254831f7793abbad795c203d4f1bbc47929b1
https://github.com/llvm/llvm-project/commit/8e7254831f7793abbad795c203d4f1bbc47929b1
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/SocketConnector.h
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
Log Message:
-----------
[orc-rt] Reject non-socket descriptors in socket:adopt (#226354)
The socket connector now checks with getsockopt(SO_TYPE) that the
descriptor named by a socket:adopt spec is a socket before wrapping it
in a SocketHandle. Non-sockets (pipes, files, etc.) are rejected with an
error and left open. Sockets are claimed after verification so that they
can be closed on error paths (e.g. if GetAttachInfo fails).
Adds SocketConnectorTest.
Commit: 7a732b1ccfbf9694aad53817ebd47d29335590bc
https://github.com/llvm/llvm-project/commit/7a732b1ccfbf9694aad53817ebd47d29335590bc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/cmake/OrcRTTesting.cmake
A orc-rt/test/regression/README.md
R orc-rt/test/regression/check-rt-process-info.test
R orc-rt/test/regression/darwin/lit.local.cfg
R orc-rt/test/regression/init.test
A orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
A orc-rt/test/regression/jit-free-foundations/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/delivery.test
A orc-rt/test/regression/jit-free-foundations/logging/os_log/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/no-printf-output.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/bad-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/format.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/level-off.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/jit-free-foundations/ogre-help.test
A orc-rt/test/regression/jit-free-foundations/smoke-check.test
A orc-rt/test/regression/languages/c/lit.local.cfg
A orc-rt/test/regression/languages/c/return-zero.c
R orc-rt/test/regression/linux/lit.local.cfg
M orc-rt/test/regression/lit.cfg.py
R orc-rt/test/regression/logging/lit.local.cfg
R orc-rt/test/regression/logging/os_log/delivery.test
R orc-rt/test/regression/logging/os_log/lit.local.cfg
R orc-rt/test/regression/logging/os_log/no-printf-output.test
R orc-rt/test/regression/logging/printf-backend/bad-level.test
R orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
R orc-rt/test/regression/logging/printf-backend/debug-level.test
R orc-rt/test/regression/logging/printf-backend/format.test
R orc-rt/test/regression/logging/printf-backend/level-off.test
R orc-rt/test/regression/logging/printf-backend/lit.local.cfg
R orc-rt/test/regression/logging/printf-backend/output-redirect.test
R orc-rt/test/regression/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/object-formats/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
A orc-rt/test/regression/object-formats/mach-o/lit.local.cfg
R orc-rt/test/regression/smoke-check.test
Log Message:
-----------
[orc-rt] Reorganize regression tests, add JIT'd code support (#226356)
Reorganize orc-rt/test/regression so that tests are placed by the
question they ask, rather than by the kind of input they use:
jit-free-foundations/ Tests of runtime facilities that can be
exercised without JIT'd code: ogre's command
line, process info, logging, and (in future)
connection lifecycle.
languages/<language>/ Tests that source-language constructs behave
correctly when JIT'd under the ORC runtime.
object-formats/<format>/<arch>/
Tests that object format features (e.g.
relocations, sections, and directives) are
handled correctly, written in assembly.
A README.md describes where tests should go, and the conventions for
writing them. Existing tests move into jit-free-foundations/, and
init.test is renamed to ogre-help.test to describe what it tests. The
darwin/ and linux/ directories are removed: they contained no tests, and
gated on the host rather than the runtime's target. Tests should gate on
features instead.
Add lit support for compiling and running JIT'd code:
%{jit} Runs its inputs under ogre, with llvm-jitlink as the
controller.
%{ogre} The path to ogre.
%{cc} Compiles C for the runtime's target.
%{cxx} Compiles C++ for the runtime's target.
%{mc} Assembles its input for the runtime's target, using
llvm-mc.
%{cc} and %{cxx} default to clang and clang++ from the LLVM tools
directory, and can be overridden with --param orc-rt-cc=<cc> and --param
orc-rt-cxx=<cxx> to test the runtime against output from other
compilers. %{mc} can't be overridden, so that object format tests always
check the runtime against the same assembler.
Tests that use these substitutions are gated on the llvm-jitlink,
llvm-mc, orc-rt-cc, and orc-rt-cxx features, so they are reported as
unsupported (rather than failing) when the tools aren't available.
clang, llvm-jitlink, and llvm-mc are added to the test dependencies if
they're being built alongside the runtime. Object format tests are also
gated on new target-arch=<arch> and target-object-format=<format>
features, derived from the runtime's target triple.
jit-free-foundations/ removes the %{cc}, %{cxx}, %{mc}, and %{jit}
substitutions, so that tests there can't accidentally depend on JIT'd
code.
Add languages/c/return-zero.c and object-formats/mach-o/arm64/
return-zero.s as the first tests that run JIT'd code, establishing the
pattern for each kind of test. They use llvm-jitlink's -show-jit-result
option to check that the JIT'd main actually ran and returned zero.
Commit: 79443248bd4a8bdb8ecfb0de94fa1e7bfb1b16f6
https://github.com/llvm/llvm-project/commit/79443248bd4a8bdb8ecfb0de94fa1e7bfb1b16f6
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/clang/unittests/offload-arch/BUILD.gn
Log Message:
-----------
[gn] port 6bef34a7ebbef (#226362)
Commit: 1777581615ec7a7278b87c0a11445c05e34db066
https://github.com/llvm/llvm-project/commit/1777581615ec7a7278b87c0a11445c05e34db066
Author: Vaisman <vasili.svirski at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/test/Dialect/NVGPU/invalid.mlir
Log Message:
-----------
[mlir][nvgpu] Add negative tests for invalid FP8 warpgroup MMA types (#208047)
Add negative tests for invalid FP8 type combinations in
nvgpu.warpgroup.mma.
FP8 inputs are supported for f16/f32 accumulators, but the verifier
should still reject unsupported combinations such as FP8 accumulators
and mixed FP8/non-FP8 input element types.
Tested:
llvm-lit mlir/test/Dialect/NVGPU/invalid.mlir
Commit: d9635c615c4d7b00c26d7281036bc5cf210d85fb
https://github.com/llvm/llvm-project/commit/d9635c615c4d7b00c26d7281036bc5cf210d85fb
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
Log Message:
-----------
[gn build] Port 6bef34a7ebbe (#226366)
Commit: 0ce55c6cfa837dcad4561ca7d5740e7c7cdc5154
https://github.com/llvm/llvm-project/commit/0ce55c6cfa837dcad4561ca7d5740e7c7cdc5154
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
Log Message:
-----------
[gn build] Port 9d90850fe6b0 (#226367)
Commit: 045cefb54385763d1159782ea97b95bb34ff2f2b
https://github.com/llvm/llvm-project/commit/045cefb54385763d1159782ea97b95bb34ff2f2b
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
Log Message:
-----------
[gn build] Port d0c787e447e1 (#226368)
Commit: a1c9df8e73402eac4c0b3a467e7876f3c387e408
https://github.com/llvm/llvm-project/commit/a1c9df8e73402eac4c0b3a467e7876f3c387e408
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/ABI/BUILD.gn
Log Message:
-----------
[gn build] Port f6e450004591 (#226369)
Commit: 5035ea5e1b16ba89eba76994ef50bdf0ff439840
https://github.com/llvm/llvm-project/commit/5035ea5e1b16ba89eba76994ef50bdf0ff439840
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
Log Message:
-----------
Orc: Compute the JIT DataLayout from the triple and ABI (#226316)
getDefaultDataLayoutForTarget was constructing a throwaway TargetMachine
purely to read back its cached DataLayout. Directly compute it from
the triple and ABI name instead.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: b15daae148e77f1ad2e20990094ddbeb8cc598ac
https://github.com/llvm/llvm-project/commit/b15daae148e77f1ad2e20990094ddbeb8cc598ac
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2bf16.ll
Log Message:
-----------
[AMDGPU] Add scalar_to_vector pattern for v2bf16 (#225303)
A target DAGCombine rewrites `v2bf16 = scalar_to_vector` into bitcast(any_extend),
but it only runs at -O1 and above, so at -O0 the node reaches ISel and fails to select.
Add the missing pattern, mirroring the v2f16 one, for both fake-true16 and real-true16.
Fixes: ROCM-31415
Commit: 28cbb0f0a0c4cbf5e732fa74a362e451a648d26b
https://github.com/llvm/llvm-project/commit/28cbb0f0a0c4cbf5e732fa74a362e451a648d26b
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
Log Message:
-----------
[AST] Avoid deprecated implicit `this` capture for C++20; NFC (#226142)
`OpenMPClause.h` contains a lambda with an implicit `this` capture,
which triggers the C++20 deprecation warning in many compilation units
that (transitively) include this header.
Commit: 6f44f333c3572d3ee54cdfdcba9124424b6ad1df
https://github.com/llvm/llvm-project/commit/6f44f333c3572d3ee54cdfdcba9124424b6ad1df
Author: Mian Miftah <mmiftah.duna at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
A llvm/test/Analysis/TypeBasedAliasAnalysis/merge-immutable.ll
Log Message:
-----------
[TBAA] Only keep the immutable flag if both merged tags have it (#225907)
getMostGenericTBAA() can return one of the two tags unchanged, as it
does when both have the same base type and offset. If only that tag has
the immutable flag, the merged access claims that the memory is constant
on both paths. For example, after SimplifyCFG hoists two such loads, GVN
can forward a load across a store to the same location.
Keep the immutable flag only if both tags have it. Otherwise drop just
the flag and keep the rest of the tag.
Commit: cfc320ace31d7a62bfbcdbcb08191d89e8e529cf
https://github.com/llvm/llvm-project/commit/cfc320ace31d7a62bfbcdbcb08191d89e8e529cf
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/placeholder_escape.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
[UpdateTestChecks] Escape special characters more consistently (#226203)
The `{{` and `[[` character sequences have special meaning in FileCheck.
Escape these when generating check lines.
We were already doing this for `{{` in analyze tests, where this pattern
occurs e.g. for nested SCEV addrecs. Extend this to `[[`, which occurs
in IR tests due to nested array initializers for globals.
We now need to do this escaping much earlier: `[[...]]` is introduced by
the check line generalization. But even before that, `{{...}}` can be
introduced either via `--replace-value-regex` or via asm scrubbing. So
we perform this escaping right at the start now.
This also updates some AMDGPU LDS tests, which were the motivation for
this change. I've had to manually fix up those check lines one too many
times now...
Commit: 4a63d32442818fd311739ec60c0a31a8e60fe64d
https://github.com/llvm/llvm-project/commit/4a63d32442818fd311739ec60c0a31a8e60fe64d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
[Support] Remove LongOptionsUseDoubleDash from cl::ParseCommandLineOptions (#226347)
The mode (https://reviews.llvm.org/D61294), in which `-` introduces only
single-character options and `--` long ones, was added for the
binutils-style tools, which have since moved to OptTable. Its last
users, yaml2obj, obj2yaml and split-file, parse with OptTable now.
LLM-aided
Commit: 210e8f1c567bbaa1b2ac8e3fcb11b106e7b4c520
https://github.com/llvm/llvm-project/commit/210e8f1c567bbaa1b2ac8e3fcb11b106e7b4c520
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead in the waterfall loop expansion (#226300)
Commit: 6c6c968398f25c2a56705004f2eb68d21d5de900
https://github.com/llvm/llvm-project/commit/6c6c968398f25c2a56705004f2eb68d21d5de900
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/test/Transforms/AggressiveInstCombine/trunc_unreachable_bb.ll
Log Message:
-----------
[AggressiveInstCombine] Bail out on graph nodes in unreachable blocks (#226383)
TruncInstCombine::run() already skips truncs in unreachable blocks, but
the expression graph of reachable trunc can still be extended into an
unreachable block through a phi incoming value. Dead code may contain an
instruction that is its own operand, and buildTruncExpressionGraph only
breaks cycles at phi nodes, so such a cycle leaves the graph unorderable
and ReduceExpressionGraph asks for the reduced value of a node it has
not built yet.
Solution: Bail out as soon as a graph node is found in an unreachable
block, which extends the existing rule from the trunc itself to the
whole graph.
Fixes #58008.
Commit: 67f685af1b364056fd59fc42841d7f428d46ee1a
https://github.com/llvm/llvm-project/commit/67f685af1b364056fd59fc42841d7f428d46ee1a
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic.c
A clang/test/CIR/CodeGen/builtin-memcpy.c
M clang/test/CIR/CodeGen/libc.c
M clang/test/CIR/CodeGen/union-copy-move-assignment.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-bit-cast.cpp
Log Message:
-----------
[CIR] Lower __builtin_memcpy/mempcpy to cir.libc.memcpy (#225845)
These previously were lowered to a call to undefined memcpy function
which caused link failures when compiled for AMDGPU since there it is
never resolved to a library function.
cir.libc.memcpy is later lowered to llvm.memcpy intrinsic call which
matches classic codegen.
This also adds alignment attributes to cir.libc.memcpy op so resulting
LLVM IR also has them just like LLVM IR produced by the classic codegen
Assisted by: claude
Commit: d9a236056a778276b286d6df818fecc5766603a6
https://github.com/llvm/llvm-project/commit/d9a236056a778276b286d6df818fecc5766603a6
Author: Ralf Jung <post at ralfj.de>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/docs/UndefinedBehavior.md
Log Message:
-----------
LangRef: mention that willreturn can cause time-traveling UB (#214229)
I think with #192992, the only remaining possible source of
time-traveling UB in LLVM are `willreturn` annotations emitted by the
frontend. So let's add a note about that.
I think ideally we'd also say somewhere "UB cannot time-travel except if
you put `willreturn` on a function that has observable behavior", but I
am not sure what would be a good place for that.
Cc @nikic @dtcxzyw @gonzalobg
Commit: fe1f8494628afdd4252fc607d7bccafa2fb64b35
https://github.com/llvm/llvm-project/commit/fe1f8494628afdd4252fc607d7bccafa2fb64b35
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
A clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add processor definition for GR765 (#225638)
Add support for the GR765 processor from Frontgrade Gaisler.
https://www.gaisler.com/products/gr765
Assisted-by: Codex
Commit: 6a9a95bf0c62cccbffed5b481b40cdbae8a5c959
https://github.com/llvm/llvm-project/commit/6a9a95bf0c62cccbffed5b481b40cdbae8a5c959
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[Analysis][NFC] Address review comments from PR #213013 (#225800)
Commit: cf8ce56a1f39f9a771d03aeedd9d89475e72a659
https://github.com/llvm/llvm-project/commit/cf8ce56a1f39f9a771d03aeedd9d89475e72a659
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocFast.cpp
A llvm/test/CodeGen/X86/regallocfast-implicit-def-live-out.mir
Log Message:
-----------
RegAllocFast: Mark unspilled implicit_def physreg defs dead (#226295)
When a virtual register defined by an IMPLICIT_DEF is live out of the
block, or reloaded below, defineVirtReg deliberately skips the spill.
If there is also no use of the value in the block, the resulting physreg
def has no reader at all, but was left without a dead flag.
This avoids some unnecessary churn between regalloc runs on AMDGPU.
Since RA runs multiple times, missed dead flags in the first RA run get
re-inferred by the later runs which this avoids.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: f131c8c21397e19c439070070348c17cc3ca2112
https://github.com/llvm/llvm-project/commit/f131c8c21397e19c439070070348c17cc3ca2112
Author: ilia-cher <30845429+ilia-cher at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/lirp.mir
Log Message:
-----------
[AMDGPU] Use CFG in LIRP tests (#226260)
LIRP tests (llvm/test/CodeGen/AMDGPU/lirp.mir) use live intervals with
gaps and redefinitions.
With added -verify-machineinstrs, current test examples trigger machine
code check failure ("Multiple connected components in live interval").
This PR updates the tests to use CFG (loops with loop-carried vregs)
similar to the real world use cases, to fix the verification, and also
simplifies the tests a bit (using implifit defs and kills).
Test:
```
ninja -C build
ninja -C build check-llvm
./build/bin/llvm-lit -v llvm/test/CodeGen/AMDGPU/lirp.mir
```
Commit: 6bfa1c552ea19edad20a76c773f480175ef58797
https://github.com/llvm/llvm-project/commit/6bfa1c552ea19edad20a76c773f480175ef58797
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/sys/select.yaml
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/pselect6.h
M libc/src/sys/select/CMakeLists.txt
M libc/src/sys/select/linux/CMakeLists.txt
A libc/src/sys/select/linux/pselect.cpp
M libc/src/sys/select/linux/select.cpp
A libc/src/sys/select/pselect.h
M libc/test/src/sys/select/CMakeLists.txt
A libc/test/src/sys/select/pselect_test.cpp
Log Message:
-----------
[libc] Implement pselect in sys/select (#226237)
Implement the standard POSIX.1-2008 / POSIX.1-2024 function `pselect` in
`<sys/select.h>`, bringing `<sys/select.h>` to 100% POSIX completion.
Fixes #226195.
Commit: 1306a7839d3eb573ff155fea66ee13e97cabf814
https://github.com/llvm/llvm-project/commit/1306a7839d3eb573ff155fea66ee13e97cabf814
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
Log Message:
-----------
[RISCV] Fix scalable expandload lowering for i8 types (#225141)
This PR adds tests for scalable expandload/compressstore intrinsics, and
also fixes a crash where we tried to query getVectorNumElements on a
scalable vector for i8 element types.
We need to use vrgatherei16 when VLMAX may exceed 255, so compute this
for scalable vectors based off of getRealMaxVLen.
This is in preparation for compress pattern vectorization support in
https://github.com/llvm/llvm-project/pull/214491
Commit: 7bcd6b42a9250baab46ad735d0c4bb4d43e74c37
https://github.com/llvm/llvm-project/commit/7bcd6b42a9250baab46ad735d0c4bb4d43e74c37
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
Log Message:
-----------
[RISCV] Return cost for scalable compressstore/expandload intrinsics (#225143)
The type based cost still needs fixed.
Commit: 74c5a6421b6bb260ef09e6d5f941970ae55629ce
https://github.com/llvm/llvm-project/commit/74c5a6421b6bb260ef09e6d5f941970ae55629ce
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Remove getMaxLMULForFixedLengthVectors. NFC (#226111)
The value can no longer be overridden after
https://github.com/llvm/llvm-project/pull/207312. Now there's nothing
specific about it to fixed vectors, so just inline it.
Commit: f17893d88ac11a34fc26dacd78f18bde2836334b
https://github.com/llvm/llvm-project/commit/f17893d88ac11a34fc26dacd78f18bde2836334b
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/src/__support/OSUtil/linux/syscall_wrappers/chmod.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
Log Message:
-----------
[libc] Fix chmod syscall arguments and add symlink test (#226144)
Our Linux chmod wrapper had two bugs in how it invoked syscalls:
- the fchmodat syscall only takes three arguments (dfd, filename, mode),
but we were passing four (with a trailing 0 for flags).
- for fchmodat2, we were (mistakenly) passing AT_SYMLINK_NOFOLLOW, even
though chmod is specified to follow symlinks.
I reorder the checks to prefer fchmodat2 (with flags=0) if available,
and otherwise invoke fchmodat with the three arguments it expects.
I also add a test to verify that chmod follows symlinks and updates the
target file's permissions, and that attempting to chmod a dangling
symlink fails with ENOENT.
Assisted-by: Gemini
Commit: 6c5ea9581684f5a819aa1691f30ae410d2a24df4
https://github.com/llvm/llvm-project/commit/6c5ea9581684f5a819aa1691f30ae410d2a24df4
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/FileCheck/FileCheckTest.cpp
Log Message:
-----------
[LLVM] Fix typo "CxtI" (#226137)
LLVM had many instances of both "CxtI" and "CtxI". This patch
standardizes on the latter. I regard the former as a mistake that should
never have spread. In general usage, "ctx" is much more common as an
abbreviation for "context".
Same for "CxtF" and "CxtPhi" which occurred a few times each.
Also fix the few instances of "Cxt" to "Ctx", which was already
overwhelmingly more common.
Commit: b202c00d967c22f5d4d83561024690f1de05bc01
https://github.com/llvm/llvm-project/commit/b202c00d967c22f5d4d83561024690f1de05bc01
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/unit/Histogram.py
Log Message:
-----------
[lit] Include zero-duration tests in the --time-tests histogram (#226132)
`--time-tests` treated an elapsed time of 0 as missing, so they were
omitted from the histogram. That made time-tests.py flaky when FileCheck
expected every test to be listed.
The PR also avoids log(0) when every recorded time is zero.
Fixes
https://github.com/llvm/llvm-project/pull/208444#issuecomment-5805067757.
Commit: 54e14c19be73548fd0c990bc3aac6d9204f3ebf8
https://github.com/llvm/llvm-project/commit/54e14c19be73548fd0c990bc3aac6d9204f3ebf8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/test/unit/support/ErrorTest.cpp
Log Message:
-----------
[orc-rt] Make Expected's move operations conditionally noexcept. (#226393)
Expected<T>'s move constructor and move assignment operator are now
noexcept whenever T's storage type is nothrow-move-constructible.
Error's move operations are already noexcept, so this is the only
condition under which moving an Expected can throw.
This allows callables that take Expected<T> by value to be stored in
noexcept-qualified move_only_functions: is_nothrow_invocable includes
the initialization of by-value parameters, which previously used
Expected's potentially-throwing move constructor.
Commit: 0a0e0fa181cf162bcc93be85abf2b1b911027e73
https://github.com/llvm/llvm-project/commit/0a0e0fa181cf162bcc93be85abf2b1b911027e73
Author: yahia <yahia.a.abdrabou at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_pton.cpp
A libc/src/arpa/inet/inet_pton.h
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_pton_test.cpp
Log Message:
-----------
Implement inet_pton (#224644)
Implement the `inet_pton` function for `IPV4` and its unit tests.
Assisted-by: gemini
Commit: 1cc5657c4ff663f1284d8a4ba4ef156e4b1664ae
https://github.com/llvm/llvm-project/commit/1cc5657c4ff663f1284d8a4ba4ef156e4b1664ae
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
Log Message:
-----------
[lldb-dap] Create telemetry data only when built with telemetry. (#225785)
I am exploring fuzzing some parts of lldb-dap. but there is a fixed
amount of memory lldb-dap can use before the fuzzing stops to catch
memory leaks.
The telemetry dispatcher always creates telemetry regardless of if lldb
is built with telemetry enabled.
`SBStructuredData::SetFromJSON` adds the telemetry string to the
ConstString pool for every request and grows lldb-dap's memory usage
rapidly.
Commit: 91d5a537b6b2b62eb1d3dbc5c9c358d2d699ff26
https://github.com/llvm/llvm-project/commit/91d5a537b6b2b62eb1d3dbc5c9c358d2d699ff26
Author: Bruno De Fraine <bruno.defraine at globalfoundries.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/CMakeLists.txt
M clang/lib/CIR/CMakeLists.txt
M clang/tools/cir-opt/CMakeLists.txt
Log Message:
-----------
[clang] Drop explicit -Woverloaded-virtual build option (#225359)
Nowadays, Clang and GCC have reasonable (and aligned) default
`-Woverloaded-virtual` warnings when using `-Wall`. Fall back to this
default and omit the more aggressive `-Woverloaded-virtual` warnings
only present in GCC's level 2 mode of the warning.
The motivation for this change is discussed in the following RFC:
https://discourse.llvm.org/t/rfc-drop-explicit-woverloaded-virtual-clang-build-option/91857
Removing the explicit `-Woverloaded-virtual` build option also allows
removing the workaround from e1bd39c.
Commit: 1735c1018def10b48b8bc1c0f6875737ae0fd9da
https://github.com/llvm/llvm-project/commit/1735c1018def10b48b8bc1c0f6875737ae0fd9da
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
A llvm/test/Instrumentation/SanitizerCoverage/missing_dbg_stack_depth.ll
Log Message:
-----------
[SanitizerCoverage] Split test (NFC) (#226405)
So these tests can actually be regenerated without heavy manual
editing.
Commit: d9dbd9671c1f2481727a9015d7fa23129a7c396d
https://github.com/llvm/llvm-project/commit/d9dbd9671c1f2481727a9015d7fa23129a7c396d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
Log Message:
-----------
[VPlan] Only retain NSW when possible in getFlagsFromIndDesc. (#226315)
getFlagsFromIndDesc is used to get the flags to use for wide inductions.
Those are normalized to Adds, with the step negated if the induction
binop is Sub.
Only retain all flags for Add. For Sub, never retain NUW and only keep
NSW if the step is known to not be signed min.
Alive2 Proofs showing incorrect NUW/NSW transfer and transfer of NSW if
step is != signed INT_MIN: https://alive2.llvm.org/ce/z/zGKeZg
Fixes https://github.com/llvm/llvm-project/issues/224024.
Commit: a465ac2be931ec1f21c9807434d59cb3b92d4b06
https://github.com/llvm/llvm-project/commit/a465ac2be931ec1f21c9807434d59cb3b92d4b06
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/APValue.cpp
Log Message:
-----------
[clang][NFC] Use llvm::ListSeparator in APValue::printPretty (#226125)
Instead of the manual `First` flag tracking.
Commit: 81e2e4474b3eb6a06e4269b97c7d33c561a3f14f
https://github.com/llvm/llvm-project/commit/81e2e4474b3eb6a06e4269b97c7d33c561a3f14f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
Log Message:
-----------
[SCEV] Set BTC to zero, if constant max BTC < BECountIfTaken. (#226098)
If ConstantMaxBECount < BECountIfTaken, we know that the backedge is
never taken and BTC is zero.
No changes in
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1426.
The main motivation is to remove another difference between
howManyLessThans
and howManyGreaterThans, which does not have the BECountIfBackedgeTaken
logic and would compute tighter bounds for backedges never taken.
No compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=022fdfa1e5a0b85dc785d30b17be3880768b22dc&to=475eeff40ba520620a406a3f615d660ed7c3eec0&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/226098
Commit: 99b454814e243b4d5f206d9605d3ab5b6e73f4b4
https://github.com/llvm/llvm-project/commit/99b454814e243b4d5f206d9605d3ab5b6e73f4b4
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
Log Message:
-----------
[InstrProfiling] Generate test checks (NFC) (#226409)
Commit: 41165fd5d503b4297cb1033fdeb1688ce0863b68
https://github.com/llvm/llvm-project/commit/41165fd5d503b4297cb1033fdeb1688ce0863b68
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
M llvm/test/CodeGen/X86/load-partial-dot-product.ll
Log Message:
-----------
[DAG] SimplifyMultipleUseDemandedBits - simplify ISD::SCALAR_TO_VECTOR to ISD::POISON if we don't demand 0th element (#225530)
Equivalent fold to SimplifyDemandedBits/SimplifyDemandedVectorElts
Fixes a number of minor regressions from #217185
Commit: d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
https://github.com/llvm/llvm-project/commit/d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
Log Message:
-----------
[DFSan] Generate test checks (NFC) (#226410)
Commit: af8da03a34ba80c310b9253c4cb062fdfdd5a143
https://github.com/llvm/llvm-project/commit/af8da03a34ba80c310b9253c4cb062fdfdd5a143
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/lib/bedrock/NativeDylibManager.cpp
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
M orc-rt/tools/ogre/ogre.cpp
Log Message:
-----------
[orc-rt] Make more Session callbacks noexcept. (#226385)
Session's OnDisconnectFn, OnDetachFn, and OnShutdownFn callbacks should
not throw exceptions.
Commit: f4620e36f5d06df795fda3ef4fd421509609ca5a
https://github.com/llvm/llvm-project/commit/f4620e36f5d06df795fda3ef4fd421509609ca5a
Author: Andrew Ng <andrew.ng at sony.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M lld/ELF/MarkLive.cpp
M lld/test/ELF/why-live.test
Log Message:
-----------
[LLD][ELF] Skip symbols to dead mergeable section pieces for --why-live (#226238)
Before this change, `--why-live=*` in "why-live.test" incorrectly prints
`live symbol: b.o:(dead)`.
Commit: 75811754a2e6c846543354358317ee02c32c2ce4
https://github.com/llvm/llvm-project/commit/75811754a2e6c846543354358317ee02c32c2ce4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/ScalarizeFunctionResult.cpp
Log Message:
-----------
[mlir][Tensor] Stop using `getAttrs()` and only copy discardable call attributes explicitly (#226412)
Preserve discardable metadata when recreating a typed direct call; its
builder supplies the inherent fields.
Part of #155475
Assisted-by: Codex
Commit: 728813099e29e7255e2c4ab7098297ba0eb9b320
https://github.com/llvm/llvm-project/commit/728813099e29e7255e2c4ab7098297ba0eb9b320
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCRoutineLowering.cpp
Log Message:
-----------
[mlir][OpenACC] Stop using getAttrs() and copy function properties separately (NFC) (#226414)
Copy inherent properties and discardable attributes explicitly when
staging a device function.
Part of #155475
Assisted-by: Codex
Commit: 0e232314ca9eda04abe27bc8c7cf7c10666c54c1
https://github.com/llvm/llvm-project/commit/0e232314ca9eda04abe27bc8c7cf7c10666c54c1
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Quant/Transforms/NormalizeQuantTypes.cpp
Log Message:
-----------
[mlir][Quant] Stop using Operation::getAttrs (NFC) (#226413)
Pass raw attributes separately from property storage when recreating an
operation.
Part of #155475
Assisted-by: Codex
Commit: e6115bc07692e0e9e632c88b2b4da99728d2951d
https://github.com/llvm/llvm-project/commit/e6115bc07692e0e9e632c88b2b4da99728d2951d
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
Log Message:
-----------
[AMDGPU] Make setImpSCCDefDead default to true. NFC. (#226406)
In SILowerControlFlow, in helper function setImpSCCDefDead, make
parameter IsDead default to true to match MachineOperand::setIsDead.
Commit: afa81ffa95ca08a20c28d9e9487404ea06a89c55
https://github.com/llvm/llvm-project/commit/afa81ffa95ca08a20c28d9e9487404ea06a89c55
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[mlir][LLVM] Stop using Operation::getAttrs in custom printers (NCF) (#226418)
At the moment, the assembly format for these operations mixes
discardable and inherent attributes. We should fix it. But for now, stop
using the `getAttrs()` API that is on its way to deprecation.
Part of #155475
Assisted-by: Codex
Commit: 51b1c275718891743493f3ed5d9e54d91a027e2d
https://github.com/llvm/llvm-project/commit/51b1c275718891743493f3ed5d9e54d91a027e2d
Author: John Brawn <john.brawn at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
A llvm/test/Transforms/SROA/load-store-overlap.ll
Log Message:
-----------
[SROA] Pre-split overlapping move slices within a partition (#210061)
When we have an overlapping load and store within an alloca, e.g. due to
a memmove that has been transformed into a load+store by InstCombine,
then currently SROA can't do anything with it. By pre-splitting such
loads and stores we eliminate any overlap between slices and thus SROA
can optimize them.
Commit: 581edb7b4a7cd8a274aec9ea4ce067eae4aaec70
https://github.com/llvm/llvm-project/commit/581edb7b4a7cd8a274aec9ea4ce067eae4aaec70
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
Log Message:
-----------
[mlir][XeVM] Stop using `getAttrs()`: explicitly preserve properties when cloning operations (NFC) (#226420)
Pass raw attributes and serialized properties separately through
OperationState when cloning an operation.
Part of #155475
Assisted-by: Codex
Commit: dc744d9839ca01185a9d19790f0b6bc18361d667
https://github.com/llvm/llvm-project/commit/dc744d9839ca01185a9d19790f0b6bc18361d667
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/test/Fir/fir-ops.fir
A flang/test/Integration/debug-submodule-ancestor.F90
A flang/test/Integration/debug-submodule-nested.F90
M flang/test/Integration/debug-submodule-procedure.F90
A flang/test/Lower/debug-submodule.f90
M flang/test/Transforms/debug-module-submodule-procedure.fir
A flang/test/Transforms/debug-submodule.fir
Log Message:
-----------
[flang][debug] Describe submodules in the debug info (#225852)
A submodule had no presence of its own in the debug info. Everything it
defined was attributed to the module at the root of its ancestry, so a
debugger showed one module per source file, every one of them carrying
the
name and the line of that ancestor, and it listed the variables of a
submodule as if the ancestor had declared them.
This PR describes a submodule in its own right. There are two
independent strands to it, and they meet only in that both decide which
module an entity is scoped in.
## Thread A: describing the submodule
### Recording the ancestry
A submodule is not a first class entity in FIR. It is not mangled into
the name of anything it declares in a way that distinguishes it from a
module, and its own name is unqualified, so nothing downstream could
tell `impl` of
`shapes` from a module called `impl`. Lowering now records the ancestry
on `fir.module_debug_imports`, which it already emits once for every
module and submodule it compiles:
```
fir.module_debug_imports "shapes" { }
fir.module_debug_imports "impl" in "shapes" parent "shapes" { }
fir.module_debug_imports "deep" in "shapes" parent "impl" { }
```
`ancestor_module` is the module at the root, and `parent_module` is the
one directly above, which is that same module for a first level
submodule and a submodule of it otherwise. Both are needed and neither
can be derived from
the other in a unit that compiles the submodule alone. The division
mirrors semantics, which keeps `ModuleDetails::ancestor()` and
`ModuleDetails::parent()` apart for the same reason.
### Naming
DWARF has no way to say that a module entry is a submodule, so the name
has to carry it. The submodule is named after the module at the root of
its ancestry and itself, joined with a `.`, which is what gfortran does:
```
DW_TAG_module DW_AT_name ("shapes.impl")
DW_TAG_module DW_AT_name ("shapes.deep")
```
The standard makes the pair unique among the submodules of a program,
and a `.` cannot appear in a Fortran identifier, so the result can never
be confused with a module that is really called that. A nested submodule
is named after the root and itself, not after the submodule containing
it, so `deep` of `shapes:impl` is `shapes.deep`. That too follows
gfortran, and it keeps the name independent of how deep the nesting
happens to be.
### Importing the parent
Scoping the entities of a submodule at the submodule loses something: a
submodule also has access to everything declared above it, and nothing
in the name of a module entry says so. Each submodule therefore imports
the one
directly above it:
```
DW_TAG_module DW_AT_name ("shapes.impl")
DW_TAG_imported_module DW_AT_import ("shapes")
DW_TAG_module DW_AT_name ("shapes.deep")
DW_TAG_imported_module DW_AT_import ("shapes.impl")
```
A debugger walks that chain up from wherever it is stopped, so an entity
declared anywhere above a submodule is still found by name. This is
again what gfortran emits, down to importing the immediate parent rather
than the root.
The entries hang off the compile unit rather than off any one procedure,
so that a submodule needs a single one however many procedures it holds.
That makes the compile unit name a module that names the compile unit
back, so it
is built as a recursive attribute, the same way a subprogram holding
imported entities already is. A unit that compiles no submodule is
unchanged.
## Thread B: separate module procedures
A separate module procedure is mangled with the module that declares its
interface rather than the submodule that defines it, because that is the
name its callers use:
```fortran
module shapes
interface
module function square(n) result(r) ! declared here
```
```fortran
submodule (shapes) impl
contains
module function square(n) result(r) ! defined here
```
```
DW_AT_linkage_name ("_QMshapesPsquare") ! names shapes, not impl
```
Every other entity of a submodule carries the whole chain in its uniqued
name: `_QMshapesSimplSdeepEdeep_var` names `shapes`, `impl` and `deep`
in turn. A separate module procedure names only the ancestor, so the
submodule defining it is recorded nowhere, and the procedure was
reported as belonging to the ancestor. Lowering now notes that submodule
on the function as `fir.defining_submodule`.
With that, nothing is scoped at the ancestor of a submodule any more,
and `AddDebugInfoPass::markSubmoduleAncestorsDefined` goes away. It
marked the ancestor as defined wherever a submodule was compiled, so
that the entities hanging off it could reach a compile unit; its comment
said it should go once submodules were described in their own right.
## What this looks like in a debugger
Given a module, a submodule defining its procedure, and a program
calling it:
```fortran
module subpar
interface
module subroutine hello()
end subroutine
end interface
end module subpar
```
```fortran
submodule (subpar) subkid
contains
module subroutine hello()
print *, 'hello from submodule'
end subroutine hello
end submodule subkid
```
A breakpoint on the bare name works before and after, but it now reports
where
the procedure really is, and it can be qualified that way too:
| `gdb -batch -ex 'break ...'` | before | after |
| --- | --- | --- |
| `hello` | `in subpar::hello at kid.f90:4` | `in subpar.subkid::hello
at kid.f90:4` |
| `subpar.subkid::hello` | `Function ... not defined.` | `in
subpar.subkid::hello at kid.f90:4` |
| `subpar::hello` | `in subpar::hello at kid.f90:4` | `Function ... not
defined.` |
The last row is the one to note: `break subpar::hello` stops working,
since the procedure is no longer described as belonging to `subpar`
alone. That is a deliberate change rather than a step backwards and
gfortran behaves exactly as this patch does on all three spellings, so
this brings flang into line with it rather than away from it.
The import is what keeps name lookup working from inside a submodule.
Stopped in a procedure of `submodule (par3) kid3`, which uses `pv`, `pk`
and `ptbl` from `par3` and its own `sq`:
```
(gdb) print pv $1 = 1
(gdb) print pk $1 = 5
(gdb) print ptbl $1 = (7, 8, 9)
(gdb) print sq $1 = (9, 8, 7)
```
Fixes https://github.com/llvm/llvm-project/issues/215811
Assisted By: Cursor
---------
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 771af157a35d7342a895a016f87b62b02a54aceb
https://github.com/llvm/llvm-project/commit/771af157a35d7342a895a016f87b62b02a54aceb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
Log Message:
-----------
[flang][CUDA] Stop using Operation::getAttrs in host stubs (NFC) (#226421)
Copy function properties and discardable attributes separately when
creating a host stub.
Part of #155475
Assisted-by: Codex
Commit: fb13f6fa52cbcd501b0dcac128254818e2d24214
https://github.com/llvm/llvm-project/commit/fb13f6fa52cbcd501b0dcac128254818e2d24214
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
Log Message:
-----------
[VPlan] Append recipes created via builder to worklist
(#213900)
The previous PR appended the top most created recipe to the worklist,
and this PR extends it to any other nested recipes that were created,
similar to InstCombine.
This removes the header mask in a good few more places on RISC-V as
measured on SPEC CPU 2017, e.g. for the following loop:
```c
long f(const int *p, const int *q, long n) {
long a = 0, b = 0;
for (long i = 0;; i++) {
if (p[i] && q[i]) { a += i; b += i; }
if (i + 1 == n) break;
}
return a + b;
}
```
Before:
```asm
LBB0_1:
sh2add a4, a3, a0
vsetvli a5, a2, e32, m1, ta, ma
vle32.v v16, (a4)
vmsne.vi v0, v16, 0
sh2add a4, a3, a1
vsetvli zero, zero, e64, m2, ta, ma
vmsltu.vx v16, v10, a5
vle32.v v17, (a4), v0.t
vsetvli zero, zero, e32, m1, ta, ma
vmsne.vi v17, v17, 0
vmand.mm v17, v0, v17
vmand.mm v0, v16, v17
vsetvli zero, zero, e64, m2, tu, mu
vadd.vv v8, v14, v8, v0.t
vadd.vv v12, v14, v12, v0.t
vsetvli zero, zero, e64, m2, ta, ma
vadd.vx v14, v14, a5
sub a2, a2, a5
add a3, a3, a5
bnez a2, .LBB0_1
```
After:
```asm
.LBB0_1:
sh2add a4, a3, a0
vsetvli a5, a2, e32, m1, ta, ma
vle32.v v14, (a4)
vmsne.vi v0, v14, 0
sh2add a4, a3, a1
vle32.v v14, (a4), v0.t
vmsne.vi v14, v14, 0
vmand.mm v0, v0, v14
vsetvli zero, zero, e64, m2, tu, mu
vadd.vv v8, v12, v8, v0.t
vadd.vv v10, v12, v10, v0.t
vsetvli zero, zero, e64, m2, ta, ma
vadd.vx v12, v12, a5
sub a2, a2, a5
add a3, a3, a5
bnez a2, .LBB0_1
```
We can also remove the (X && Y) | (X && !Y) -> X combine, but this is
left for another NFC PR.
Commit: 4b66c9678662933ff13f8362e3a208cbe6284808
https://github.com/llvm/llvm-project/commit/4b66c9678662933ff13f8362e3a208cbe6284808
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
Log Message:
-----------
[SDPatternMatch] Remove MatchContext. NFC (#218372)
This removes the match context templating now that trivial VP nodes are
gone.
`m_Negative` and the other computeKnownBits matchers previously used the
DAG within the match context. But they're now unused after #220527, so
this removes them. Since computeKnownBits is an expensive operation, any
combines in future that need to check the sign should likely call
computeKnownBits outside of the pattern match
Commit: a631bc15c5445e48124a06a884ecf4bf9ec491e2
https://github.com/llvm/llvm-project/commit/a631bc15c5445e48124a06a884ecf4bf9ec491e2
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/sve-vector-repeat.ll
A llvm/test/Verifier/vector-repeat-intrinsic-invalid.ll
A llvm/test/Verifier/vector-repeat-intrinsic-valid.ll
M llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
Log Message:
-----------
[IR][REVEC] Define llvm.vector.repeat intrinsic (#208212)
This intrinsic is used to repeat a <N x Ty> fixed-length vector `vscale`
times to form a <vscale x N x Ty> scalable vector. The patch adds
legalisation support and ISel for AArch64.
This intrinsic is required to support re-vectorisation of fixed-length
vectors to scalable ones, as shufflevector instructions do not support
scalable vectors. Re-vectorisation was discussed in this RFC:
https://discourse.llvm.org/t/rfc-re-vectorisation-to-wider-vectors-in-loopvectorizer/91071
Assisted-by: codex (tests)
Commit: 22312472de3ef8b4c5318da0b527510c5d498ae9
https://github.com/llvm/llvm-project/commit/22312472de3ef8b4c5318da0b527510c5d498ae9
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/IR/Verifier.cpp
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
A llvm/test/Verifier/byval-scalable.ll
Log Message:
-----------
[IR] Reject a scalable byval argument in the verifier (#226170)
A byval argument is copied into the caller's frame, and the current
implementation needs the size of that copy at compile time, which a
scalable type does not have. Plain `llc` fails on such IR today, and
SafeStack crashed on it in #182759. Nothing in the tree produces it and
no target needs it yet, so rather than teach SafeStack to step around it
(#225067), disallow it in the LangRef and reject it in the verifier
until the necessary support exists. `isScalableTy()` also covers a
struct with a scalable member.
Fixes #182759.
Commit: ffcb13aadde867aca18819f8716972afaccf124f
https://github.com/llvm/llvm-project/commit/ffcb13aadde867aca18819f8716972afaccf124f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
Log Message:
-----------
Orc: Move getDefaultDataLayoutForTarget out of line (#226416)
Try to fix link errors with shared library builds.
Commit: 3897817145ffa3204e2593cb0b26c535724221c2
https://github.com/llvm/llvm-project/commit/3897817145ffa3204e2593cb0b26c535724221c2
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
Log Message:
-----------
[AArch64][CostModel] Consider some nxv1 operations as legal (#214471)
This is allowing some operations on vscale x 1 types, namely:
- load/store
- masked load/store
- arithmetic instructions like add/sub/mul
For those, there is already codegen coverage. See e.g.
- llvm/test/CodeGen/AArch64/sve-int-arith.ll
- llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
- llvm/test/CodeGen/AArch64/sve-masked-gather.ll
- llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
These types are relevant for enabling REVEC in LoopVectorizer. For
AArch64, the main target there is turning NEON vector sizes into SVE
vector size, i.e. using VF = "vscale x 1". For loops with mixed vector
and scalar types, we'll want to allow vectorising scalar types with such
a VF.
Commit: 55b498466a7b2620d09fcdf1b2300f71a35f6d8b
https://github.com/llvm/llvm-project/commit/55b498466a7b2620d09fcdf1b2300f71a35f6d8b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
Log Message:
-----------
[clang][bytecode] Stop relying on `CheckEvaluationResult()` (#186045)
We already have to do a lot of check in `EvaluationResult` ourselves, only to redo some of them on the `APValue` we create. Just do all the checks before creating the `APValue` in the first place.
Commit: 76c1ac4608e9cabf9e27e95094f7cd11dcc8ebcb
https://github.com/llvm/llvm-project/commit/76c1ac4608e9cabf9e27e95094f7cd11dcc8ebcb
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 0a0e0fa (#226400)
This fixes 0a0e0fa181cf162bcc93be85abf2b1b911027e73 (#224644).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e34e31190233a5733d6b7751160a29e50cd8b41c
https://github.com/llvm/llvm-project/commit/e34e31190233a5733d6b7751160a29e50cd8b41c
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGStmtOpenMP.cpp
A clang/test/OpenMP/target_map_address_space_codegen.c
Log Message:
-----------
[clang][OpenMP] Cast by-reference captures to the address space of the captured field (#226229)
Fixes #140069
Sema strips all qualifiers, including the address space, from the type
of a variable captured by an OpenMP region, so the outlined function for
a `target` region takes `int __seg_gs a;` as a plain `int &`, i.e. a
pointer in the default address space. That is the intended model: inside
the region the variable is an ordinary object, and the host's segment
address space means nothing on a device. `GenerateOpenMPCapturedVars`
ignored the captured field's type for by-reference captures though, and
passed the variable's own address. With `map(alloc: a)` that is a `ptr
addrspace(256)` argument for a `ptr` parameter, and emitting the host
fallback call tripped the "Calling a function with a bad signature"
assertion. The same call is emitted on the `omp_offload.failed` path
when offloading targets are given, so this wasn't limited to host-only
compiles.
By-reference captures now convert the address to the type of the
captured field, adding an `addrspacecast` only when the address spaces
differ. On x86 the cast doesn't change the pointer value, so the region
gets the linear address of the object, which is also what the mapping
passes to the runtime and what GCC does for the same code. Captures
whose address already has the right type are untouched.
Commit: c6c8f3006f378079cf2c89e4e4bddc0adb15f8ea
https://github.com/llvm/llvm-project/commit/c6c8f3006f378079cf2c89e4e4bddc0adb15f8ea
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for aa6b03e (#226426)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=aa6b03ed5a9ffe5ba6f0d945fac9961884b5c6ed
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: b7c4b2171d5f4e902dad4b207625bc08c45e8cbf
https://github.com/llvm/llvm-project/commit/b7c4b2171d5f4e902dad4b207625bc08c45e8cbf
Author: Tomas Matheson <Tomas.Matheson at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
A llvm/test/Transforms/Attributor/callback-noalias.ll
M llvm/test/Transforms/Attributor/callbacks.ll
M llvm/test/Transforms/OpenMP/parallel_deletion.ll
Log Message:
-----------
[Attributor] Check callback broker argument aliases correctly (#218672)
Fix a bug in AANoAliasCallSiteArgument. AbstractCallSite uses separate
callback argument and broker operand numbers. Example:
```llvm
call void @broker(
ptr @callee, # broker arg 0
ptr %slot, # broker arg 1
ptr %slot # broker arg 2
) !callback !0
define internal void @callee(
ptr align 8 dereferenceable(8) %a, # callback arg 0
ptr align 8 dereferenceable(8) %b # callback arg 1
) {
```
In `mayAliasWithArgument`, `OtherArgNo` is the broker (call-site) arg
number (0, 1 or 2), so it should be compared against
`getCallSiteArgNo()` not `getCalleeArgNo()`. Otherwise it will compare
the argument with itself, and skip some comparisons with other args, and
wrongly infer/fail to infer `noalias`.
Commit: 02f6eaf60dcc3794ed563c0d3953de2d029f024f
https://github.com/llvm/llvm-project/commit/02f6eaf60dcc3794ed563c0d3953de2d029f024f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
Log Message:
-----------
[SLP]Extract vectorized source of gathered sub-fields
The bitcast emitted for gathered sub-fields used the source scalar
directly, even if it was vectorized and erased, causes the crash,
register the bitcast as an external user of the vectorized source.
Fixes the crash reported in #224919.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/226437
Commit: a98f7ed68ea1cbe43a6786a68c3f9f2e1b9cceb7
https://github.com/llvm/llvm-project/commit/a98f7ed68ea1cbe43a6786a68c3f9f2e1b9cceb7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
Log Message:
-----------
AMDGPU: Mark SCC def dead in init exec lowering (#226373)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: a8250aacd1436752d3862005155e611da512710e
https://github.com/llvm/llvm-project/commit/a8250aacd1436752d3862005155e611da512710e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
Log Message:
-----------
AMDGPU: Mark SCC def dead in wave reduction expansions (#226370)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 0ebe3a65e87819ff5068f21fb5a6615b3d580e64
https://github.com/llvm/llvm-project/commit/0ebe3a65e87819ff5068f21fb5a6615b3d580e64
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/abs-mul-buildvector-in-loop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop-schedule.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-keep-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim-combined.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-copyable-in-another-entry.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-flattened-copyable-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
Log Message:
-----------
[SLP]Cancel scheduling of the trimmed nodes
The nodes, trimmed during throttling, are not vectorized, but their
bundles were still scheduled by the final scheduling.
Cancel these bundles before the final scheduling, recalculate the
dependencies and schedule their scalars as separate instructions, so
they keep their original order and stay close to their users, which
helps instructions scheduler and save some time for bundles scheduling.
Assisted-by: Cursor
Reviewers: bababuck, RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/226268
Commit: 57e112ccb2a509c0e1d36963b187fccdd59566de
https://github.com/llvm/llvm-project/commit/57e112ccb2a509c0e1d36963b187fccdd59566de
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/IR/RuntimeLibcalls.cpp
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
Log Message:
-----------
RuntimeLibcalls: Describe register-returning divmod libcall ABIs (#217825)
Teach RuntimeLibcallsInfo::getFunctionTy about the ARM AEABI
(__aeabi_*divmod) and Windows (__rt_*div*) divmod signatures. Currently
the custom lowering to these calls hardcodes the call signature
information, but in the future this should be automatically handled.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
https://github.com/llvm/llvm-project/commit/2fe83ee7dc5bb40e2f15e164c21a01bec01c1792
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
Log Message:
-----------
SystemZ: Mark unread CC defs dead at build time (#226434)
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 4e50049d9d5b44028c9cca9763f6ceeda1c667fb
https://github.com/llvm/llvm-project/commit/4e50049d9d5b44028c9cca9763f6ceeda1c667fb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding CF pseudos (#226249)
The control flow pseudos start with dead flags on the implicit scc def,
but did not transfer to the replacement instruction
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
Commit: 319529bbe0ef99a5262fef91317e1327fa1e8453
https://github.com/llvm/llvm-project/commit/319529bbe0ef99a5262fef91317e1327fa1e8453
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
Log Message:
-----------
AMDGPU: Mark the SCC def dead when expanding 64-bit scalar add/sub (#226269)
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 01b8b4dfc99e46273b9811cb4663a90c2fb61676
https://github.com/llvm/llvm-project/commit/01b8b4dfc99e46273b9811cb4663a90c2fb61676
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Remove variable only used in assert (#226433)
This caused a buildbot failure after the variable was introduced in #208212
Commit: 0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
https://github.com/llvm/llvm-project/commit/0e7fb8bcf11a59d564bf45d0568d528bf1e9bdcf
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
Log Message:
-----------
[mlir][vector] Support fixed-size masks in `eliminateVectorMasks` (#221595)
`eliminateVectorMasks` returned immediately unless a `VscaleRange` was
supplied. The TODO above that early return argued the fixed-size case
was unlikely to be useful, because "for fixed-size code dimensions are
all static so masks tend to fold away".
That is only true when the mask operand is constant. When it comes from
an induction variable, which is what tiling produces, the operand is not
constant and no fold removes the mask, even though value-bounds analysis
can prove it all-true. For example, `-canonicalize` leaves this alone:
```mlir
scf.for %i = %c0 to %c1024 step %c4 {
%rem = arith.subi %c1024, %i : index
%mask = vector.create_mask %rem : vector<4xi1>
%v = vector.transfer_read %t[%i], %f0, %mask : tensor<1024xf32>, vector<4xf32>
...
}
```
`%i <= 1020`, so `%rem >= 4` and the mask is all-true.
The algorithm was never scalable-specific; only the bound query was.
This makes `vscaleRange` genuinely optional: without one, the lower
bound is computed with `ValueBoundsConstraintSet::computeConstantBound`
and compared against the mask dimension. Scalable dimensions still need
a range and bail without one, so a fixed-size caller cannot prove a
dimension whose runtime size is `vscale` times the size in the type. The
scalable path is unchanged, and the existing test still passes with its
RUN line untouched.
### Behaviour change for downstream callers
An omitted `vscaleRange` used to make the call a no-op. It now runs the
fixed-size analysis.
No in-tree caller relies on the old meaning, but IREE does call this
unconditionally in `Codegen/Common/GenericVectorization.cpp`, passing
`getDefaultVscaleRange()`, which returns `std::nullopt` for every target
other than AArch64+SVE. For those targets this patch turns a no-op into
live mask elimination. That is the intended benefit, but it is worth
knowing before the next integrate. The added cost is bounded: constant
and `vscale`-multiple operands short-circuit before any analysis, so
only `create_mask` ops with unknown operands pay for a bound query.
### Tests
New `eliminate-masks-fixed-size.mlir`, run through a `fixed-size` option
added to the test pass: two cases that are eliminated (the tiled loop
above, and a dynamic operand bounded by `arith.maxsi`) and three that
are not (an unbounded operand, a lower bound smaller than the mask
dimension, and a scalable dimension with no vscale range). Each negative
was checked to fail for the stated reason, by making the smallest change
that flips it.
Context:
https://discourse.llvm.org/t/rfc-should-vector-transfer-read-write-keep-in-bounds-measurements-on-the-masking-alternative/91649
Assisted-by: Claude
Commit: 675c1cfa5d925232db882942674a40de41654bc5
https://github.com/llvm/llvm-project/commit/675c1cfa5d925232db882942674a40de41654bc5
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
Log Message:
-----------
[LLVM][CodeGen] Enable the AArch64PTrueCoalescing pass. (#225830)
Fixes https://github.com/llvm/llvm-project/issues/137040
Commit: 68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
https://github.com/llvm/llvm-project/commit/68a9cd31fd277f9f6b8a8ab95e18d00a786e7c12
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
Log Message:
-----------
[Polly] Detect preconditions of cached user assumption translations (#226204)
`addUserAssumptions` detected preconditions of a user assumption by
checking whether building its condition recorded new assumptions, but
`SCEVAffinator` caches translated expressions, so a precondition shared
with an earlier assumption (e.g. the same truncation) was missed and the
assumption went into the context, removing the runtime check it relied
on. For example, with `__builtin_assume((signed char)n >= 0)` and
`__builtin_assume((signed char)n < 10)`, the `n >= 128` check was
dropped, although `n = 261` satisfies both assumptions. Instead, check
the invalid domain of each assumption, which is also cached, and if it
is non-empty, add the assumption to the defined behavior context as in
#189350.
Assisted-by: Claude (Anthropic)
Commit: 940105295f88426cb85b01b075f44f36a90c12fd
https://github.com/llvm/llvm-project/commit/940105295f88426cb85b01b075f44f36a90c12fd
Author: Sergey Semenov <sergey.semenov at intel.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/sycl-tests.yml
Log Message:
-----------
[CI][libsycl] Enable -Werror in libsycl precommit testing (#226129)
Commit: 952fa726ae35661f86ea92ed989d0efa36e69c7f
https://github.com/llvm/llvm-project/commit/952fa726ae35661f86ea92ed989d0efa36e69c7f
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
M clang/test/CodeGen/AArch64/sve/len.c
Log Message:
-----------
[clang][AArch64] Consolidate codegen tests for SVE's LEN intrinsics (#226131)
This patch completes the migration of the tests from:
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
to:
* clang/test/CodeGen/AArch64/sve/len.c
`len.c` covers all the cases previously tested by `acle_sve_len.c`.
However, unlike `acle_sve_dup.c`, it was only tested as C. Add `-x c++`
RUN lines to provide the equivalent C++ coverage, including lowering
via CIR.
Commit: f1c5f1e98cac5bf9d688272f2137da992ab005da
https://github.com/llvm/llvm-project/commit/f1c5f1e98cac5bf9d688272f2137da992ab005da
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
Log Message:
-----------
[orc-rt] Make BootstrapInfo construction noexcept. (#226459)
These methods should never throw.
Commit: df26d549b9115ff7c32b6fb9031250994d0f3515
https://github.com/llvm/llvm-project/commit/df26d549b9115ff7c32b6fb9031250994d0f3515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
ARM: Use divmod type signatures from RuntimeLibcallsInfo (#217869)
Start moving towards an API to emit calls from RuntimeLibcallsInfo's
knowledge about the type signature of a function instead of manually
computing an IR type from the EVT of the operation.
Also change the swap of arguments to be based on the libcall impl,
rather than the ABI since it's logically a property of the function
itself.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: dcdeeebef2ef008326211b661cfb81d1d35b4086
https://github.com/llvm/llvm-project/commit/dcdeeebef2ef008326211b661cfb81d1d35b4086
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/LoongArch/pr177863.ll
A llvm/test/CodeGen/X86/vec_setcc-3.ll
Log Message:
-----------
[DAG] SimplifySetCC - adjust setcc result type when peeking through truncates (#226422)
For the "(setcc (trunc x) (trunc y)) -> (setcc x y)" fold with non vXi1
cmp result type, make sure we adjust the type and then trunc/extend it
correctly using BooleanContent.
Fixes #226365
Commit: a509a4e98a50a2acc172a5f6eba77b8df020e3cd
https://github.com/llvm/llvm-project/commit/a509a4e98a50a2acc172a5f6eba77b8df020e3cd
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/flifetime-safety-c.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
Log Message:
-----------
[LifetimeSafety] Enable C support by default under -Wlifetime-safety (#224028)
This PR extends the lifetime safety analysis to C. When the analysis is
enabled with `-Wlifetime-safety`, it now also runs on C code without the
extra `-fexperimental-lifetime-safety-c` flag.
I have renamed `-fexperimental-lifetime-safety-c` to
`-flifetime-safety-c` since it is on by default from now on. The
`-fno-lifetime-safety-c` flag disables the analysis for C. I have
updated the documentation and the release notes and rewrote the RUN
lines of the test cases that used the old flag.
Commit: b60afea0d31f4da34b9d867a00817a0e53dbdb05
https://github.com/llvm/llvm-project/commit/b60afea0d31f4da34b9d867a00817a0e53dbdb05
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
Log Message:
-----------
[SimplifyCFG] Keep a debug location on calls cloned by `FoldBranchToCommonDest` (#224247)
Fixes #220848
When folding a branch to a common destination, SimplifyCFG clones the
bonus instructions into the predecessor and resets their debug
locations, so the debugger doesn't step onto code from a branch that
wasn't taken. It did that with `setDebugLoc(DebugLoc::getDropped())` for
every instruction. That's fine for an `icmp`, but with
`-bonus-inst-threshold=2` a `speculatable` call can be a bonus
instruction too, and an inlinable call in a function with debug info
must have a `!dbg` location, otherwise the inliner can't set up the
inlined-at scope. The verifier rejects the module with "inlinable
function call in a function with debug info must have a !dbg location".
The clone now uses `Instruction::dropLocation()`, which is what
`speculativelyExecuteBB` in the same file already does. Non-call
instructions still lose their location as before, while calls get a line
0 location in the function's scope, so nothing misleading shows up when
stepping and the IR stays valid. `dropLocation()` needs the parent
function, so the clone is inserted into the predecessor before its
location is updated. An earlier attempt at this swap (674f57870f4c) was
reverted after buildbot crashes; the clone was still unparented when
`dropLocation()` ran there, which would explain them.
Commit: eae3e9e64de82ae5a162783808c89521cfea7742
https://github.com/llvm/llvm-project/commit/eae3e9e64de82ae5a162783808c89521cfea7742
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Fix move_only_function storing references to lvalue callables. (#226474)
move_only_function's converting constructor instantiated CallableImpl
with the deduced forwarding-reference type, so constructing from an
lvalue callable stored a reference to it rather than a copy, leaving the
move_only_function dangling once the original went out of scope.
This commit decays the callable type before instantiating CallableImpl,
and adds a static_assert to CallableImpl to enforce that it's only
instantiated with decayed types.
Commit: 176a24691b1b315cfd0f15ee8bb8adcc086683be
https://github.com/llvm/llvm-project/commit/176a24691b1b315cfd0f15ee8bb8adcc086683be
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M clang/docs/SourceBasedCodeCoverage.md
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/test/profile/instrprof-api.c
Log Message:
-----------
[docs][clang] Document additional public profile runtime APIs (#224424)
Android's code coverage runtime started using these functions recently,
and I noticed they were undocumented (and the reviewer highlighted
that `instr_prof_interface.h` exists).
So this commit:
- Moves their declarations to that header
- Updates `SourceBasedCodeCoverage.md` to highlight that header
- Adds quips to said `.md` file for these functions
An LLM was used to take a first pass at this; I reviewed and refined.
Commit: 8de4cb45931adab063265b565408ff2b72be668d
https://github.com/llvm/llvm-project/commit/8de4cb45931adab063265b565408ff2b72be668d
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M orc-rt/test/unit/support/move_only_function-test.cpp
Log Message:
-----------
[orc-rt] Tighten move_only_function ShouldCopyInitialize test. (#226483)
ShouldCopyInitialize only checked that constructing a move_only_function
from an lvalue didn't move the callable, so it passed when the callable
was held by reference and never copied at all.
This commit replaces the moved flag with copy and move counters, and
checks that construction performs exactly one copy and no moves.
Commit: 83589c854329a8366672f9932ee27b422902038f
https://github.com/llvm/llvm-project/commit/83589c854329a8366672f9932ee27b422902038f
Author: google-yfyang <yfyang at google.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
Log Message:
-----------
Fix Bazel build for 0a0e0fa (#226489)
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=0a0e0fa181cf162bcc93be85abf2b1b911027e73
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 84d75c8ab6eb610cde0048458f96085f923fc392
https://github.com/llvm/llvm-project/commit/84d75c8ab6eb610cde0048458f96085f923fc392
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[AArch64] Make compiling arm_neon.h faster (#226378)
Replace two linear scans with map lookups.
On my system, reduces time to compile a TU that does nothing but
`#include <arm_neon.h>` from 92.0 ms ± 1.4 ms to 70.9 ms ± 1.3 ms.
No behavior change.
Commit: 290f1bef4b9df1f1629c35a6926a32bb1701952f
https://github.com/llvm/llvm-project/commit/290f1bef4b9df1f1629c35a6926a32bb1701952f
Author: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx/build-at-commit/action.yml
M .github/workflows/sycl-tests.yml
M bolt/test/X86/dwarf5-debug-names-skip-forward-decl.s
M clang/CMakeLists.txt
A clang/docs/HLSL/DynamicResources.md
M clang/docs/HLSL/HLSLDocs.md
M clang/docs/LifetimeSafety.md
M clang/docs/ReleaseNotes.md
M clang/docs/SourceBasedCodeCoverage.md
M clang/docs/analyzer/checkers.md
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/HLSLExternalSemaSource.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ByteCode/ByteCodeEmitter.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/EvalEmitter.h
M clang/lib/AST/ByteCode/EvaluationResult.cpp
M clang/lib/AST/ByteCode/EvaluationResult.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/AST/ExprConstShared.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/CMakeLists.txt
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl.h
M clang/lib/Headers/hlsl/hlsl_detail.h
A clang/lib/Headers/hlsl/hlsl_resources.h
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/HeuristicResolver.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLambdaCapturesChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefSafetyModel.cpp
M clang/test/AST/ByteCode/builtin-functions.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/references.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
A clang/test/AST/HLSL/DynamicResources-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
M clang/test/AST/HLSL/matrix-alias.hlsl
M clang/test/Analysis/Checkers/WebKit/mock-canborrow.h
A clang/test/Analysis/Checkers/WebKit/unborrowed-lambda-captures.cpp
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic.c
A clang/test/CIR/CodeGen/builtin-memcpy.c
M clang/test/CIR/CodeGen/libc.c
M clang/test/CIR/CodeGen/union-copy-move-assignment.cpp
M clang/test/CIR/CodeGenBuiltins/builtin-bit-cast.cpp
R clang/test/ClangScanDeps/build-session-validation-relocated-modules.c
M clang/test/ClangScanDeps/modules-relocated-mm-macro.c
R clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_len.c
M clang/test/CodeGen/AArch64/sve/len.c
A clang/test/CodeGenCXX/GH176161.cpp
M clang/test/CodeGenCXX/global-init.cpp
M clang/test/CodeGenHLSL/builtins/InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedExchange.hlsl
M clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
A clang/test/CodeGenHLSL/resources/dynamic-resources.hlsl
A clang/test/Driver/flifetime-safety-c.c
A clang/test/Driver/print-enabled-extensions/riscv-gaisler-gr765.c
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note/riscv.c
A clang/test/OpenMP/target_map_address_space_codegen.c
M clang/test/Sema/LifetimeSafety/annotation-suggestions-fixits.c
M clang/test/Sema/LifetimeSafety/safety-c.c
M clang/test/SemaCXX/PR19955.cpp
M clang/test/SemaCXX/cxx2c-expansion-stmts.cpp
M clang/test/SemaCXX/paren-list-agg-init.cpp
A clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedExchangeFloat-sm60.hlsl
M clang/test/SemaHLSL/BuiltIns/InterlockedExchange-errors.hlsl
M clang/test/SemaHLSL/Language/InitLists.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources-availability.hlsl
A clang/test/SemaHLSL/Resources/dynamic-resources.hlsl
M clang/tools/cir-opt/CMakeLists.txt
M clang/unittests/Sema/HeuristicResolverTest.cpp
M compiler-rt/include/profile/instr_prof_interface.h
M compiler-rt/lib/asan/asan_globals_win.cpp
M compiler-rt/lib/asan/asan_win.cpp
M compiler-rt/lib/asan/asan_win_common_runtime_thunk.h
M compiler-rt/lib/profile/InstrProfiling.h
M compiler-rt/lib/sanitizer_common/sanitizer_win_defs.h
M compiler-rt/lib/sanitizer_common/sanitizer_win_thunk_interception.cpp
M compiler-rt/test/profile/instrprof-api.c
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp
M flang/test/Fir/fir-ops.fir
A flang/test/Integration/debug-submodule-ancestor.F90
A flang/test/Integration/debug-submodule-nested.F90
M flang/test/Integration/debug-submodule-procedure.F90
A flang/test/Lower/Intrinsics/mvbits-unsigned.f90
A flang/test/Lower/debug-submodule.f90
M flang/test/Transforms/debug-module-submodule-procedure.fir
A flang/test/Transforms/debug-submodule.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/arpa/inet.yaml
M libc/include/sys/select.yaml
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/chmod.h
A libc/src/__support/OSUtil/linux/syscall_wrappers/pselect6.h
M libc/src/__support/net/CMakeLists.txt
M libc/src/__support/net/address.cpp
M libc/src/__support/net/address.h
M libc/src/arpa/inet/CMakeLists.txt
A libc/src/arpa/inet/inet_pton.cpp
A libc/src/arpa/inet/inet_pton.h
M libc/src/sys/select/CMakeLists.txt
M libc/src/sys/select/linux/CMakeLists.txt
A libc/src/sys/select/linux/pselect.cpp
M libc/src/sys/select/linux/select.cpp
A libc/src/sys/select/pselect.h
M libc/src/sys/stat/linux/CMakeLists.txt
M libc/test/src/arpa/inet/CMakeLists.txt
A libc/test/src/arpa/inet/inet_pton_test.cpp
M libc/test/src/sys/select/CMakeLists.txt
A libc/test/src/sys/select/pselect_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
M libc/test/src/sys/stat/chmod_test.cpp
M libcxx/include/__locale_dir/locale_base_api.h
M libcxx/include/__locale_dir/locale_base_api/bsd_locale_fallbacks.h
M libcxx/include/__locale_dir/num.h
M libcxx/include/__locale_dir/support/aix.h
M libcxx/include/__locale_dir/support/bsd_like.h
M libcxx/include/__locale_dir/support/fuchsia.h
M libcxx/include/__locale_dir/support/linux.h
M libcxx/include/__locale_dir/support/newlib.h
M libcxx/include/__locale_dir/support/no_locale/strtonum.h
M libcxx/include/__locale_dir/support/openbsd.h
M libcxx/include/__locale_dir/support/windows.h
M libcxx/src/support/win32/locale_win32.cpp
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/test-at-commit
M libsycl/src/CMakeLists.txt
A libsycl/test/basic/linux-rpath.test
M libsycl/test/lit.cfg.py
M lld/ELF/MarkLive.cpp
M lld/test/ELF/why-live.test
M lldb/include/lldb/Target/Process.h
M lldb/source/Expression/UserExpression.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/ObjectFile/wasm/ObjectFileWasm.cpp
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Utility/Policy.cpp
M lldb/test/API/macosx/expedited-recent-reads/TestExpeditedRecentReads.py
M lldb/test/API/macosx/expedited-stack-memory/main.c
A lldb/test/Shell/ObjectFile/wasm/data-segment-names.yaml
A lldb/test/Shell/ScriptInterpreter/Python/nested_command_selected_target.test
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/LLDBUtils.h
M lldb/unittests/Utility/PolicyTest.cpp
M llvm/docs/CommandLine.md
M llvm/docs/LFI.md
M llvm/docs/LangRef.md
M llvm/docs/ReleaseNotes.md
M llvm/docs/UndefinedBehavior.md
M llvm/include/llvm/Analysis/ConstantFolding.h
M llvm/include/llvm/Analysis/InstructionSimplify.h
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/include/llvm/Analysis/TargetFolder.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MIRParser/MIParser.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/GSYM/GsymCreator.h
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/Transforms/InstCombine/InstCombiner.h
M llvm/include/llvm/Transforms/Scalar/JumpThreading.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/StaticDataProfileInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AllocationOrder.cpp
M llvm/lib/CodeGen/AllocationOrder.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/RegAllocFast.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
M llvm/lib/DebugInfo/GSYM/GsymCreator.cpp
M llvm/lib/ExecutionEngine/Orc/JITTargetMachineBuilder.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCPseudoProbe.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64PTrueCoalescing.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/DirectX/DXILLegalizePass.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCLFIRewriter.h
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
A llvm/lib/Target/X86/X86LFIRewritePass.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/IPO/AttributorAttributes.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/MergeICmps.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPTypeUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
M llvm/test/Analysis/CostModel/AArch64/sve-arith.ll
M llvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-expandload-compressstore.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/trip-count13.ll
A llvm/test/Analysis/TypeBasedAliasAnalysis/merge-immutable.ll
M llvm/test/CodeGen/AArch64/constant-pool-partition.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/jump-table-partition.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/masked-srem-scalable.ll
M llvm/test/CodeGen/AArch64/masked-urem-scalable.ll
M llvm/test/CodeGen/AArch64/sve-bf16-combines.ll
M llvm/test/CodeGen/AArch64/sve-bf16-int-converts.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AArch64/sve-lsrchain.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
M llvm/test/CodeGen/AArch64/sve-partial-reduce-wide-add.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
A llvm/test/CodeGen/AArch64/sve-vector-repeat.ll
M llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
M llvm/test/CodeGen/AArch64/vector-absolute-difference.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_mul_one.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
M llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-merge.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/lirp.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.anti-hints.mir
M llvm/test/CodeGen/AMDGPU/loop_break.ll
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-clear-kills.mir
M llvm/test/CodeGen/AMDGPU/lower-i1-copies-implicit-def-unstructured-loop.mir
M llvm/test/CodeGen/AMDGPU/mmra.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
A llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2bf16.ll
M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
M llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
M llvm/test/CodeGen/AMDGPU/si-init-whole-wave.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-remove-redundant-block-liveintervals.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir
M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
A llvm/test/CodeGen/AMDGPU/vopd3-f64-opy-last-vgpr-gfx1250.mir
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat-unsupported-width.ll
A llvm/test/CodeGen/DirectX/LegalizeAtomicExchangeFloat.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicExchangeFloat.ll
M llvm/test/CodeGen/LoongArch/pr177863.ll
A llvm/test/CodeGen/MIR/AMDGPU/register-allocation-antihints-mir-print-parse.mir
M llvm/test/CodeGen/RISCV/machine-sink-jumptable-edge-split.ll
M llvm/test/CodeGen/RISCV/rvv/compressstore.ll
M llvm/test/CodeGen/RISCV/rvv/expandload.ll
R llvm/test/CodeGen/RISCV/sifive-interrupt-attr-err.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
M llvm/test/CodeGen/RISCV/sifive-interrupt-frame-flags.ll
A llvm/test/CodeGen/RISCV/sifive-interrupt-frame-pointer.ll
M llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
M llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
A llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
M llvm/test/CodeGen/X86/bfloat.ll
M llvm/test/CodeGen/X86/dag-topological-sort.ll
A llvm/test/CodeGen/X86/fast-isel-call-frame-dead-eflags.ll
M llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll
M llvm/test/CodeGen/X86/global-variable-partition.ll
A llvm/test/CodeGen/X86/lfi-align.ll
M llvm/test/CodeGen/X86/load-partial-dot-product.ll
A llvm/test/CodeGen/X86/regallocfast-implicit-def-live-out.mir
A llvm/test/CodeGen/X86/vec_setcc-3.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
M llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
M llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
M llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
A llvm/test/Instrumentation/SanitizerCoverage/missing_dbg_stack_depth.ll
A llvm/test/MC/X86/LFI/control-flow-errors.s
A llvm/test/MC/X86/LFI/control-flow.s
M llvm/test/Transforms/AggressiveInstCombine/trunc_unreachable_bb.ll
A llvm/test/Transforms/Attributor/callback-noalias.ll
M llvm/test/Transforms/Attributor/callbacks.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
M llvm/test/Transforms/LoopStrengthReduce/AArch64/vscale-fixups.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-scalable-vectorization-always.ll
M llvm/test/Transforms/LoopVectorize/AArch64/invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization-cost-tuning.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/countable-early-exit-no-epilogue.ll
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-complex-mask.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/OpenMP/parallel_deletion.ll
M llvm/test/Transforms/PGOProfile/data-access-profile.ll
M llvm/test/Transforms/PhaseOrdering/X86/avg.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
A llvm/test/Transforms/SCCP/fastmath-flags.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/abs-mul-buildvector-in-loop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/div.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/fma-reduce-regression.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/lcssa-phi-extract-scale.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/recalc-copyable-deps-on-reorder.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop-schedule.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-keep-drop.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-satd.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-store-chain.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/buildvector-all-external-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/partial-vec-invalid-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reordered-buildvector-scalars.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-extracts.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim-combined.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/splat-gather-trim.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/wide-load-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/deleted-instructions-clear.ll
M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
M llvm/test/Transforms/SLPVectorizer/X86/external-bin-op-user.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracted-subfields.ll
M llvm/test/Transforms/SLPVectorizer/X86/gathered-loads-non-full-reg.ll
M llvm/test/Transforms/SLPVectorizer/X86/lookahead.ll
M llvm/test/Transforms/SLPVectorizer/X86/original-inst-scheduled-after-copyable.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-copyable-in-another-entry.ll
M llvm/test/Transforms/SLPVectorizer/X86/reassoc-flattened-copyable-operand.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
M llvm/test/Transforms/SLPVectorizer/X86/select-copyable-cmp-poison.ll
M llvm/test/Transforms/SLPVectorizer/X86/split-node-reorder-node-with-ops.ll
M llvm/test/Transforms/SLPVectorizer/X86/subvector-minbitwidth-unsigned-value.ll
M llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
A llvm/test/Transforms/SROA/load-store-overlap.ll
A llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-call-debugloc.ll
A llvm/test/Transforms/Util/DeclareRuntimeLibcalls/divmod.ll
A llvm/test/Verifier/byval-scalable.ll
A llvm/test/Verifier/vector-repeat-intrinsic-invalid.ll
A llvm/test/Verifier/vector-repeat-intrinsic-valid.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/placeholder_escape.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/placeholder_escape.test
A llvm/test/tools/llvm-gsymutil/X86/macho-last-symbol-section-end.yaml
A llvm/test/tools/llvm-readobj/ELF/RISCV/eflags-abi.test
M llvm/tools/llc/lib/llcdriver.cpp
M llvm/tools/llvm-gsymutil/llvm-gsymutil.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/AllocationOrderTest.cpp
M llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
M llvm/unittests/CodeGen/SelectionDAGNodeConstructionTest.cpp
M llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
M llvm/unittests/FileCheck/FileCheckTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/offload-arch/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Target/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/ABI/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
M llvm/utils/lit/lit/main.py
M llvm/utils/lit/lit/util.py
A llvm/utils/lit/tests/unit/Histogram.py
M mlir/include/mlir/Dialect/Vector/Transforms/VectorTransforms.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/OpImplementation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRoutineLowering.cpp
M mlir/lib/Dialect/Quant/Transforms/NormalizeQuantTypes.cpp
M mlir/lib/Dialect/Tensor/Transforms/ScalarizeFunctionResult.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorMaskElimination.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/Dialect/Linalg/one-shot-bufferize-analysis.mlir
M mlir/test/Dialect/Linalg/one-shot-bufferize.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/Tensor/one-shot-bufferize.mlir
M mlir/test/Dialect/Vector/eliminate-masks.mlir
M mlir/test/Dialect/Vector/one-shot-bufferize.mlir
M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-format.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
M offload/include/OpenMP/OMPT/Callback.h
M offload/include/OpenMP/OMPT/Interface.h
M offload/include/device.h
M offload/liboffload/src/OffloadImpl.cpp
M offload/libompaccsupport/PluginManager.cpp
M offload/libompaccsupport/device.cpp
M offload/libomptarget/OffloadRTL.cpp
M offload/libomptarget/OpenMP/OMPT/Callback.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M openmp/runtime/test/affinity/no_leak_with_disabled.c
M orc-rt/cmake/OrcRTTesting.cmake
M orc-rt/include/orc-rt/bedrock/BootstrapInfo.h
M orc-rt/include/orc-rt/bedrock/Session.h
M orc-rt/include/orc-rt/bedrock/SocketConnector.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/move_only_function.h
M orc-rt/lib/bedrock/BootstrapInfo.cpp
M orc-rt/lib/bedrock/NativeDylibManager.cpp
M orc-rt/lib/bedrock/sys/posix/SocketConnector.cpp
A orc-rt/test/regression/README.md
R orc-rt/test/regression/check-rt-process-info.test
R orc-rt/test/regression/darwin/lit.local.cfg
R orc-rt/test/regression/init.test
A orc-rt/test/regression/jit-free-foundations/check-rt-process-info.test
A orc-rt/test/regression/jit-free-foundations/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/delivery.test
A orc-rt/test/regression/jit-free-foundations/logging/os_log/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/os_log/no-printf-output.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/bad-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-compiled-out.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/debug-level.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/format.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/level-off.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/lit.local.cfg
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/output-redirect.test
A orc-rt/test/regression/jit-free-foundations/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/jit-free-foundations/ogre-help.test
A orc-rt/test/regression/jit-free-foundations/smoke-check.test
A orc-rt/test/regression/languages/c/lit.local.cfg
A orc-rt/test/regression/languages/c/return-zero.c
R orc-rt/test/regression/linux/lit.local.cfg
M orc-rt/test/regression/lit.cfg.py
R orc-rt/test/regression/logging/lit.local.cfg
R orc-rt/test/regression/logging/os_log/delivery.test
R orc-rt/test/regression/logging/os_log/lit.local.cfg
R orc-rt/test/regression/logging/os_log/no-printf-output.test
R orc-rt/test/regression/logging/printf-backend/bad-level.test
R orc-rt/test/regression/logging/printf-backend/debug-compiled-out.test
R orc-rt/test/regression/logging/printf-backend/debug-level.test
R orc-rt/test/regression/logging/printf-backend/format.test
R orc-rt/test/regression/logging/printf-backend/level-off.test
R orc-rt/test/regression/logging/printf-backend/lit.local.cfg
R orc-rt/test/regression/logging/printf-backend/output-redirect.test
R orc-rt/test/regression/logging/printf-backend/runtime-level.test
A orc-rt/test/regression/object-formats/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/lit.local.cfg
A orc-rt/test/regression/object-formats/mach-o/arm64/return-zero.s
A orc-rt/test/regression/object-formats/mach-o/lit.local.cfg
R orc-rt/test/regression/smoke-check.test
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/CommonTestUtils.h
M orc-rt/test/unit/bedrock/SessionTest.cpp
A orc-rt/test/unit/bedrock/SocketConnectorTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCAOverSocketTest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
M orc-rt/test/unit/support/move_only_function-test.cpp
M orc-rt/tools/ogre/ogre.cpp
M polly/lib/Analysis/ScopBuilder.cpp
A polly/test/ScopInfo/user-assumption-cached-precondition.ll
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/zGoldthorpe/wide-copies/precommit
Commit: 322e0ce4438a76534e5be6b3e11d5bbe0e016c08
https://github.com/llvm/llvm-project/commit/322e0ce4438a76534e5be6b3e11d5bbe0e016c08
Author: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-09-25 (Fri, 25 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
Log Message:
-----------
Remove direct subregister `COPY`s
Compare: https://github.com/llvm/llvm-project/compare/5440497602e9...322e0ce4438a
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