[all-commits] [llvm/llvm-project] 0d049f: [RegAlloc] Add register allocation anti-hints infr...

[Syadus Sefat via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0d049f14804d436b12d81846de00c45516541f0b
      https://github.com/llvm/llvm-project/commit/0d049f14804d436b12d81846de00c45516541f0b
  Author: Syadus Sefat <42645939+mssefat at users.noreply.github.com>
  Date:   2026-09-24 (Thu, 24 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/AllocationOrder.cpp
    M llvm/lib/CodeGen/AllocationOrder.h
    M llvm/lib/CodeGen/MachineRegisterInfo.cpp
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/unittests/CodeGen/AllocationOrderTest.cpp

  Log Message:
  -----------
  [RegAlloc] Add register allocation anti-hints infrastructure (#218071)

This PR adds a RA anti-hint mechanism. MachineRegisterInfo is extended
to track anti-hints
between vregs to try avoiding to be allocated on the same physical
register. AllocationOrder can
queries these and also allows the target reorder the allocation order
through the new
TargetRegisterInfo::applyRegAllocationAntiHints hook. The default
implementation moves
the anti-hinted registers to the end of the order, so they are only used
as a last option.
## Stack
PR **1/4**. Next: MIR serialization #218073.



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