[all-commits] [llvm/llvm-project] a88189: [AMDGPU][NFC] Compute prologue frame size/alignmen...
Adam Smith via All-commits
all-commits at lists.llvm.org
Wed Sep 23 10:35:00 PDT 2026
Branch: refs/heads/users/adams381/cir-callconv-nonbyval-param-noload
Home: https://github.com/llvm/llvm-project
Commit: a88189669034268827befe9bb65880a31e91778d
https://github.com/llvm/llvm-project/commit/a88189669034268827befe9bb65880a31e91778d
Author: ahradwan2-public <ahmedwahab1997 at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Log Message:
-----------
[AMDGPU][NFC] Compute prologue frame size/alignment in 64-bit (#224734)
In `SIFrameLowering::emitPrologue` the stack-realignment sequence computes its
`S_AND` mask (`-Alignment * scale`), `S_ADD` offset (`(Alignment-1) * scale`)
and the final SP adjustment (`RoundedSize * scale`) from 32-bit locals; the
multiply is done in 32 bits, which CodeGen static analysis flags as a possible
truncation (`cpp/integer-multiplication-cast-to-long`). Widen `NumBytes`,
`RoundedSize` and Alignment to 64-bit. The `AsmPrinter` still truncates via
`printImmediate32`, so emitted asm is unchanged; only the raw MIR immediate of
the realign `S_AND_B32` changes (e.g. `4294443008 -> -524288`). The seven
autogenerated .mir frame tests are regenerated accordingly.
Assisted-by: Cline
Commit: de734ce70b5e9c3c4eeca4306394c1bec1c30f84
https://github.com/llvm/llvm-project/commit/de734ce70b5e9c3c4eeca4306394c1bec1c30f84
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/finalize-isel-vadd-co-u32-dead-carry.mir
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
Log Message:
-----------
AMDGPU: Preserve carry-out dead flag in V_ADD_CO_U32 custom inserter (#225736)
EmitInstrWithCustomInserter rebuilds V_ADD/SUB_CO_U32_e32 but did
not carry over the dead flag. Preserve the flag to reduce implicitly
depending on dead flags recomputed by LiveVariables.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 68d3c25ee618d057ef16cea97b34dc2b85d46118
https://github.com/llvm/llvm-project/commit/68d3c25ee618d057ef16cea97b34dc2b85d46118
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/test/CIR/CodeGen/side-effect.cpp
A clang/test/CIR/Transforms/abi-lowering/memory-effects-argmem-indirect.cir
A clang/test/CIR/Transforms/abi-lowering/memory-effects-argmem.cir
Log Message:
-----------
[CIR] Widen memory effects for ABI argument memory (#221067)
A const or pure callee that the ABI rewrites to take an sret slot or a
byval pointer reaches argument memory whatever the source declared, and
a variadic callee does too since its declared parameters do not cover
every argument. CallConvLowering was leaving memory_effects untouched,
so LowerToLLVM emitted memory(none) or memory(read) for functions that
do touch that memory.
CallConvLowering now sets arg_mem to readwrite on #cir.memory_effects
once it knows the signature, and does the same at a call site when the
call passes a slot.
Assisted-by: Cursor / claude-opus-5
Commit: 0601a126c256e09faea980045ac0b787b49dfe39
https://github.com/llvm/llvm-project/commit/0601a126c256e09faea980045ac0b787b49dfe39
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
Log Message:
-----------
[clang][bytecode] Short-circuit inelegible functions when compiling (#225618)
Don't bother setting up parameter maps for functions we know we won't
compile.
Commit: 0e718a81c3a564de6c4c7193c1bd748f7f96eb29
https://github.com/llvm/llvm-project/commit/0e718a81c3a564de6c4c7193c1bd748f7f96eb29
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
A llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
Log Message:
-----------
[AMDGPU] Add BarrierLatency mutations to CoexecSched (#200954)
Change-Id: Id86bbdb427b23f68d39ceee196e4232e91974186
Commit: 2711c15ebeda051a6b3f974c217bb50fdf3bfce2
https://github.com/llvm/llvm-project/commit/2711c15ebeda051a6b3f974c217bb50fdf3bfce2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.h
Log Message:
-----------
[clang][bytecode] Add a CheckLoad overload taking a PtrView (#225741)
We sometimes create intermediate pointers, which always insert
themselves into the pointer list of a block. Which is slow.
This adds a `CheckLoad()` overload taking a `PtrView`, which we can use
in those cases.
Commit: a4ebc09e5b3337c24cad8cb65e88e8af7977aaf1
https://github.com/llvm/llvm-project/commit/a4ebc09e5b3337c24cad8cb65e88e8af7977aaf1
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/test/CIR/CodeGen/base-init-eh.cpp
M clang/test/CIR/CodeGen/ctor-null-init.cpp
M clang/test/CIR/CodeGen/delegating-ctor.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit.cpp
M clang/test/CIR/CodeGen/global-ptr-init.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
M clang/test/CIR/CodeGen/multi-vtable.cpp
M clang/test/CIR/CodeGen/rtti-member-pointer.cpp
M clang/test/CIR/CodeGen/rtti-qualfn.cpp
M clang/test/CIR/CodeGen/vbase.cpp
M clang/test/CIR/CodeGen/virtual-function-calls.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/CodeGenCXX/base-layout.cpp
M clang/test/CIR/CodeGenCXX/vtable-pure-deleted-funcs.cpp
Log Message:
-----------
[CIR] Fixup tests after GEP type changed (#225770)
CIR tests with OGCG check lines for GEPs changed to use i8 instead of a
different type in many cases. This patch fixes it. This is from #225415
Every fix ended up moving OGCG closer to what CIR does, so this is a
generally good thing.
Commit: 93236c1e0296ff92f04b38d37ae927673be9f536
https://github.com/llvm/llvm-project/commit/93236c1e0296ff92f04b38d37ae927673be9f536
Author: dong jianqiang <dongjianqiang2 at huawei.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/ELF_aarch64.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
A llvm/test/ExecutionEngine/JITLink/AArch64/ELF_ehframe_be.s
A llvm/test/ExecutionEngine/JITLink/AArch64/ELF_relocations_be.s
Log Message:
-----------
[JITLink] Support AArch64 big-endian (BE8) ELF objects (#225120)
The AArch64 ELF backend hard-coded ELF64LE, so aarch64_be
objects failed to load. Follow the PPC64 multi-endian pattern:
the graph builder, aarch64::applyFixup, ELFJITLinker_aarch64,
and the link entry points (link_ELF_aarch64 / link_ELF_aarch64_be)
are templated on llvm::endianness, with data fixups written in the
compile-time target endianness and instructions always little-endian
(the A64 ISA is word-invariant).
Commit: 6d617b831f5b9f354753106f6ffe5fc482209756
https://github.com/llvm/llvm-project/commit/6d617b831f5b9f354753106f6ffe5fc482209756
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M flang/lib/Lower/IO.cpp
A flang/test/Lower/io-implied-do-collapse.f90
Log Message:
-----------
[Flang] add support for collapsed io calls for implicit do loops (#212646)
This is a extension of the work done in #163945 by addind support for IO
lowering to recognize a contiguous single-level io-implied-do in an
unformatted transfer with no condition specifiers, and collapse it into
a single array-section descriptor call instead of emitting a per-element
fir.do_loop.
see RFC:
https://discourse.llvm.org/t/rfc-add-support-for-collapsed-io-calls-for-implicit-do-loops/91416/2
Assisted-by: Opus 4.8
Commit: 8489203ec846d08db23532530419748de09c3374
https://github.com/llvm/llvm-project/commit/8489203ec846d08db23532530419748de09c3374
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
A flang/test/Transforms/licm-acc-captured-ref.fir
A flang/test/Transforms/licm-acc-compute-only.fir
A flang/test/Transforms/licm-scope.fir
Log Message:
-----------
[flang] Support scoped LICM and OpenACC capture provenance (#225401)
Follow compute-region capture operands when checking whether scalar and
scalar-descriptor loads are safe to speculate. Preserve the existing
optional, array-element, and loop-modification safety checks.
Add an optional only-inside operation-name selector while retaining
function-scoped alias analysis. Resolve the name once per function and
compare interned operation names during ancestor traversal. The default
continues to select all loops. An explicit name selects loops with a
matching ancestor within the function, including the function itself.
Cover capture safety, host exclusion, non-OpenACC and nested scopes,
loop boundaries, unmatched names, and the function boundary.
The motivation for this is to allow running LICM only on device relevant
loop at O0.
Commit: 6e6507c6c32917f228a0497fae83ab9d2d3dddf6
https://github.com/llvm/llvm-project/commit/6e6507c6c32917f228a0497fae83ab9d2d3dddf6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
Log Message:
-----------
[MLGO] Update tests after #220090 (#225811)
PR #220090 changed quite a bit some of the costs/default behaviors which
manifested in test failures for the dev mode logging tests.
Commit: bed99cbb50b83f8cdd87f273aee4d6b99dd67a9d
https://github.com/llvm/llvm-project/commit/bed99cbb50b83f8cdd87f273aee4d6b99dd67a9d
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
R flang/test/Transforms/licm-acc-captured-ref.fir
R flang/test/Transforms/licm-acc-compute-only.fir
R flang/test/Transforms/licm-scope.fir
Log Message:
-----------
Revert "[flang] Support scoped LICM and OpenACC capture provenance" (#225813)
Reverts llvm/llvm-project#225401
Breaks shared library builds.
Commit: f79899f140e5a02a733a8c8d1cf456d658a3739a
https://github.com/llvm/llvm-project/commit/f79899f140e5a02a733a8c8d1cf456d658a3739a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-pr-benchmark.yml
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
Log Message:
-----------
[libc++] Encode Lit configuration parameters in machines.json (#225601)
Instead of hardcoding a bunch of Lit parameters in run-benchmarks,
encode them in machines.json and thread them through. This makes
machines.json closer to being the authoritative place describing the
full benchmark configuration.
Commit: 71db60ced71917b09aaf117d900fadad4bb9e343
https://github.com/llvm/llvm-project/commit/71db60ced71917b09aaf117d900fadad4bb9e343
Author: Christian Krause <chris at christiankrause.de>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
A llvm/test/CodeGen/Mips/fpu-delay-in-delay-slot.ll
M llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
M llvm/test/CodeGen/Mips/llvm-ir/load.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
A llvm/test/CodeGen/Mips/mips1-fpu-load-delay.ll
Log Message:
-----------
[Mips] Respect FPU hazards on MIPS-I to MIPS-III (#223411)
On the oldest MIPS processors the hardware does not wait for a value
loaded from memory to arrive before it runs the next instruction: the
compiler has to leave a one-instruction gap itself. It already did this
for whole-number loads, but not for floating-point ones, so float code
could read the register a moment too early and quietly compute with a
stale value. This change makes the compiler treat floating-point loads
and moves off the math unit the same way it treats whole-number loads,
fixing that silent wrong answer. Newer chips are unaffected: they wait
on their own, and no gap is added for them.
GCC models both of these: [ISA_HAS_LOAD_DELAY and
ISA_HAS_XFER_DELAY](https://github.com/gcc-mirror/gcc/blob/5115c7e447fc07457443df874bf57840e8316d5f/gcc/config/mips/mips.h#L1322-L1334)
in mips.h, and the [hazard/can_delay
attributes](https://github.com/gcc-mirror/gcc/blob/5115c7e447fc07457443df874bf57840e8316d5f/gcc/config/mips/mips.md#L756-L789).
I used Opus 5 (Anthropic) as an assistant while preparing this patch. I
did the investigation and diagnosis myself, reviewed and tested every
change, and verified the GCC source references above against the actual
GCC source before linking them.
Commit: a14634f662776d7c9f3fe15f5eb687dc6287d17c
https://github.com/llvm/llvm-project/commit/a14634f662776d7c9f3fe15f5eb687dc6287d17c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-test-tools.yml
Log Message:
-----------
Partially Reapply "[libcxx] Move premerge jobs to k8s mode runner set (#221395)" (#225222)
This reverts commit 5dc57157f12f0ff676e823d9b4d98b45c07e5df2.
Fetching tags for some reason causes `actions/checkout` to fail more
often than not. It turns out we don't need that for any of the libc++
workflows, so just disable it on top of the revert and things should be
working.
Commit: 36f7f848d562a410b21e14cf077a0631d76f0a98
https://github.com/llvm/llvm-project/commit/36f7f848d562a410b21e14cf077a0631d76f0a98
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/test/tools/llvm-offload-wrapper/coff-opt-ref.ll
Log Message:
-----------
[Offloading] Use getGetElementPtr() overload accepting DataLayout (#225766)
To produce constant GEP in canonical ptradd representation.
Commit: a5ba2cf8b46ddaf6690b5b74b2863e4bc76f12a9
https://github.com/llvm/llvm-project/commit/a5ba2cf8b46ddaf6690b5b74b2863e4bc76f12a9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/store-chain-leading-slice-wider-vf.ll
Log Message:
-----------
[SLP][NFC]Add a test with the regressed vectorization (2 vs 4 before), NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225819
Commit: 3eecc4081d4ee225eda7375eee9f79e065f3c411
https://github.com/llvm/llvm-project/commit/3eecc4081d4ee225eda7375eee9f79e065f3c411
Author: Diego Novillo <dnovillo at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/test/CodeGen/SPIRV/debug-info/debug-declare-dbg-value-variadic.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-declare.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-dbg-value.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant-existing-type.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-cross-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-merge-region.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-module-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-postlegalizer-order.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-typedef-cycle.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-unsupported.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value.ll
Log Message:
-----------
[SPIRV] Emit NonSemantic DebugValue (#224158)
This adds support for emitting `DebugValue` in
`SPIRVNonSemanticDebugHandler` for `DBG_VALUE` records.
NOTE: Much of the new code was necessary to emit constants and their
types at module scope. I also added a bunch of tests as I started
getting into corner cases.
Since
[`DebugValue`](https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html#DebugValue)
cannot have forward references, it can only reference already emitted
instructions. `DebugValue` cannot come after merge instructions either,
and SPIR-V requires an id defined in a function block to dominate a
non-phi use. The change has four parts:
1. `analyzeDebugRecords()` resolves placement and availability before
emission begins. Each record stays at its source position unless it lies
between a merge instruction and its terminator, in which case it moves
before the merge. A register value is accepted only when its definition
dominates the record. Records without a legal value are dropped.
2. A constant assignment needs a typed SPIR-V result id, but Machine IR
carries only untyped immediates. The type comes from the variable, and
`buildConstDbgValue()` decides whether the value is sign or zero
extended. The backend reuses a module `OpConstant` with that type and
value, or emits one alongside the line and column constants.
3. Debug info must be removable without changing what the module
requires. The handler creates `OpTypeBool` and 32-bit scalar types,
which need no capability, and reuses 8, 16 and 64-bit types only when
the module already defines them. Any other constant assignment is
dropped.
5. `SPIRVPostLegalizer::generateAssignType` placed `ASSIGN_TYPE` after a
`DBG_VALUE` naming the same register, because `updateRegType()` advances
the insertion point past the debug record. This change resets the
insertion point to just after the definition, so `ASSIGN_TYPE` comes
before the record that names it.
Commit: dec20dfbe042962775095e5394b2979fde9a4f45
https://github.com/llvm/llvm-project/commit/dec20dfbe042962775095e5394b2979fde9a4f45
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
Log Message:
-----------
[AMDGPU][InstCombine] Add sudot zero/constant folding tests. NFC (#225321)
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Commit: d343b26ef687cefe30e7f8072d6befa6f2e0829d
https://github.com/llvm/llvm-project/commit/d343b26ef687cefe30e7f8072d6befa6f2e0829d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/extract-fmul-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/store-chain-leading-slice-wider-vf.ll
Log Message:
-----------
[SLP]Try the wider store slice when the leading VF=2 slice fails
With the register VF 2 the instruction count check may reject the
leading slice of a store chain.
Try the double-width slice at the same position first and keep the wider
slices for the rest of the chain once one is vectorized.
Fixes the remaining perf regression from #221717.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225823
Commit: f96f12533199911caea0ccc0fd96f18df37c8ca4
https://github.com/llvm/llvm-project/commit/f96f12533199911caea0ccc0fd96f18df37c8ca4
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-24 (Thu, 24 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
Log Message:
-----------
[AMDGPU][InstCombine] Fold constant add/sub into the dot accumulator (#225002)
`amdgcn.{s,u}dot{2,4,8}(a, b, C) +/- K -> dot(a, b, C +/- K)` when both
the
accumulator C and K are constants. The new constant is computed with
wrapping APInt arithmetic to match the non-clamping accumulate.
Only applies when clamp is false (the saturating accumulate does not
reassociate) and the dot has a single use. K - dot is left alone since
it
would need the dot product negated.
Commit: ae2e61a2b21e38fd8356931aa75baf78a64da365
https://github.com/llvm/llvm-project/commit/ae2e61a2b21e38fd8356931aa75baf78a64da365
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/ptrtoaddr-i32-index-width.ll
Log Message:
-----------
[SCEV] Fix sign bits of pointers wider than their index type. (#225786)
ComputeNumSignBits counts bits over the full pointer width. If all sign
bits are in the high bits, the code previously did not adjust the number
of signed bits. For narrow index types, this could result in the number
of sign bits > than the narrow bitwidth triggering an assert in APInt
(test example has 64 bit pointer with 16 bit index width.
If all sign bits are in the high bits outside the index width, they do
not add any information for the index, just use 1 in that case.
Fixes a crash in the added tests.
PR: https://github.com/llvm/llvm-project/pull/225786
Commit: f22fe777f37bd5b901f92fb7c7ab654711e87da5
https://github.com/llvm/llvm-project/commit/f22fe777f37bd5b901f92fb7c7ab654711e87da5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
Log Message:
-----------
[CostModel][X86] Add masked memory test coverage for VBMI2 capable CPUs (#225790)
Add tigerlake and znver4/5 coverage - znver4 is going to be a pain as it has awful compressstore perf :(
Prep work for #214613
Commit: 0f58d0420f36f3f374e3ae35f679874e0b4ff4de
https://github.com/llvm/llvm-project/commit/0f58d0420f36f3f374e3ae35f679874e0b4ff4de
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#225614)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast on
UnexpandedParameterPack::first because it is always nonnull.
Specifically, UnexpandedParameterPack is constructed only in the
following places, all of which store a nonnull pointer in first, and
first is never modified afterward:
- CollectUnexpandedParameterPacksVisitor::addUnexpanded in
SemaTemplateVariadic.cpp
- TransformLambdaExpr in TreeTransform.h
- TransformSizeOfPackExpr in TreeTransform.h
Assisted-by: Antigravity
Commit: 53e9da7812f3fa8fa79ae5e000552e1110da8da7
https://github.com/llvm/llvm-project/commit/53e9da7812f3fa8fa79ae5e000552e1110da8da7
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/AVR/AVR.h
M llvm/lib/Target/DirectX/DXILOpBuilder.h
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/Hexagon/Hexagon.h
M llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
M llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.h
Log Message:
-----------
[Target] Remove declarations without definitions (NFC) (#225615)
initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.
AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.
AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.
ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.
ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.
ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on
August 17, 2011 in commit 46dd413991f6fa74a1da3f139b386e364dfc9f78.
createAVRBranchSelectionPass: The definition was removed on July 5, 2017
in commit a24aa1990084c15f0ad27dbcff7ab1c96369f0f9.
dxil::DXILOpBuilder::getOpFunctionType: Added on August 2, 2024 in
commit 8cf85653b6f5c90b83f8a5741baad5725d6c6932 without a definition.
dxil::DXILBitcodeWriter::VSTOffsetPlaceholder,
dxil::DXILBitcodeWriter::writeIdentificationBlock,
dxil::DXILBitcodeWriter::writePerModuleFunctionSummaryRecord,
dxil::DXILBitcodeWriter::writeModuleLevelReferences,
dxil::DXILBitcodeWriter::addToStrtab,
dxil::DXILBitcodeWriter::createNamedMetadataAbbrev,
dxil::DXILBitcodeWriter::writeNamedMetadata,
dxil::DXILBitcodeWriter::pushGlobalMetadataAttachment,
dxil::DXILBitcodeWriter::writeOperandBundleTags,
dxil::DXILBitcodeWriter::writeSyncScopeNames,
dxil::DXILBitcodeWriter::writeOperandBundles,
dxil::DXILBitcodeWriter::writeGlobalValueSymbolTable: Added on
April 14, 2022 in commit f2526c1a5c6fe6d2740b68e2d73b85c958fd2719
without uses or definitions.
initializeHexagonMergeActivateWeightPass,
createHexagonMergeActivateWeight: Added on August 5, 2024 in commit
c04857cb2c9f6f2e8add61192c62e48a83938efd without definitions.
createHexagonTargetTransformInfoPass: Added on June 15, 2015 in commit
56efafc0566def51ec7e632e09574ed553296b48 without a definition.
HexagonGlobalSchedulerImpl::CanPromoteToDotNew: Added on February 20,
2026 in commit 7064ff2226141034fdb264c29b97acbc733f8dae without a
definition.
HexagonTargetLowering::LowerANY_EXTEND,
HexagonTargetLowering::LowerSIGN_EXTEND,
HexagonTargetLowering::LowerZERO_EXTEND: The definitions were removed on
February 6, 2018 in commit 8abaf8954a97f20d0fd036e8e32e4b69d23f342e.
HexagonTargetLowering::LowerEH_LABEL: Added on December 12, 2011 in
commit 1213a7a57fdcb6c875b3f79103fc96d3e9d30b40 without a definition.
HexagonPacketizerList::isCurifiable: Added on December 16, 2015 in
commit 56bbf54b4303cac8772b6d66e3bd0668f8013067 without a definition.
HexagonMCChecker::checkBranches: The definition was removed on
December 11, 2017 in commit a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.
createHexagonMCRegisterInfo: Added on February 6, 2017 in commit
8cdfe8ecf3dd14d128148c5ff0b01d74b082e3c2 without a definition.
HexagonShuffler::restrictNoSlot1: Added on January 17, 2020 in commit
c1873631d0a8f2acca4ab428a1e9abea844d97ff without a definition.
MipsAsmParser::parseImm: The definition was removed on August 8, 2016 in
commit 3feeb9c851a193f42d890b35f36816fae198860f.
MipsAsmParser::validateMSAIndex: The definition was removed on April 1,
2014 in commit b50ccf8e26653781191491aab90c7379f29bd5e1.
MipsMCCodeEmitter::getMSAMemEncoding: The definition was removed on
March 31, 2016 in commit dc0602a2c20a3f514541165a19cb1534597c5dc6.
Mips16DAGToDAGISel::initMips16SPAliasReg: The definition was removed on
June 16, 2016 in commit de7816b0cd3ffbd9775681c408298febe4c10fe3.
MipsAsmPrinter::EmitInstrWithMacroNoAT: The definition was removed on
June 2, 2012 in commit 23327b30ef9af2323dd20248e311ef454f9e0dfa.
MipsTargetLowering::emitSEL_D: The definition was removed on July 20,
2017 in commit be0bc71e023455a32d074b69054b6ffee6f1160e.
MipsSEDAGToDAGISel::selectMULT: The definition was removed on April 11,
2013 in commit 4f1130eb66ff01128c0061ace377c10b74128a45.
MipsSETargetLowering::lowerINT_TO_FP,
MipsSETargetLowering::lowerFP_TO_INT: The definitions were removed on
June 17, 2026 in commit de84e7ccc602fe2ef8b886a9b095c80d110f61a0.
MipsSubtarget::IsLinux: All uses were removed on December 19, 2014 in
commit 8985ba912f00de68f3fccf8bf440a30bf5bdb89e.
MipsSubtarget::OverrideMode, MipsSubtarget::setHelperClassesMips16,
MipsSubtarget::setHelperClassesMipsSE: All uses of OverrideMode and the
definitions of setHelperClassesMips16 and setHelperClassesMipsSE were
removed on July 18, 2014 in commit
4e7d1e7e7bb36bcd715297b36d688bdc0ed96bdf.
initializeNVVMReflectPass: The definition was removed on April 10, 2025
in commit 701d726ef09ea89909df9bd2fdc63c63758fe8d6.
NVPTXDAGToDAGISel::SelectTexSurfHandle: The definition was removed on
June 25, 2025 in commit 70333de6cfa76d2e0e36720d6065edd501a3ad8a.
NVPTXDAGToDAGISel::tryConstantFP: The definition was removed on
December 19, 2024 in commit 310e79875752886a7713911e2a1ec14bc75bd4b3.
NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorReduceCommon: The definition
was removed on August 6, 2026 in commit
1ac19e41a0674925911e88cc5218dfd95a09a3ac.
createPPCMachObjectWriter: The definition was removed on March 2, 2020
in commit 3e851f4a688c42315355aae743b403dddeba9860.
createPPCExpandISELPass: The definition was removed on August 27, 2024
in commit 8e901c255df45e38cb1d69a576804029e20868bf.
SystemZTargetLowering::convertPrevCompareToBranch: The definition was
removed on July 25, 2013 in commit
c3f85d73ab781601b2aababa8ef6572fa437c4ff.
VEAsmParser::parseCCOpOperand: Added on June 5, 2020 in commit
117c0d7c1c12e5c82e0f5498fec511e8ae08d9ca without a definition.
VEAsmParser::parseRDOpOperand: Added on June 10, 2020 in commit
34fef0c980446c3ea9595328e0e525db222870f0 without a definition.
WebAssemblyOptimizeReturnedLegacy::visitCallBase: The definition was
moved to a helper class on July 15, 2026 in commit
491539a8b801aad5706cc32fc54a319791d57a91.
X86FixupInstTuningLegacy::processInstruction: The definition was moved
to a helper class on January 12, 2026 in commit
f6d0a512972a74ef100723b9526a6a0ddb23f894.
XCoreTargetLowering::getReturnAddressFrameIndex: Added on November 7,
2008 in commit ca08e0645a9629980156208506b6ae463b746e42 without a
definition.
Assisted-by: Antigravity
Commit: 20c7e959ac021728f493a1d9aca6883b607313ee
https://github.com/llvm/llvm-project/commit/20c7e959ac021728f493a1d9aca6883b607313ee
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
Log Message:
-----------
[AMDGPU] Fix assert on empty inline asm register constraint (#225743)
An empty register name reaches this parser from user source, where
StringRef::front() asserts
Commit: d8ec5c857fded543e1daa439aae17af4cf807e8f
https://github.com/llvm/llvm-project/commit/d8ec5c857fded543e1daa439aae17af4cf807e8f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
A llvm/test/CodeGen/AMDGPU/move-scalar-carry-to-valu-dead-vcc.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
Log Message:
-----------
AMDGPU: Mark dead carry-out when rewriting scalar carry op to VALU (#225738)
If an operation is expanded with a dead scc def, the resultant vcc def
will also be dead, so preserve the dead flag. Reduces implicit reliance on
LiveVariables recomputing dead flags later.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: 8a67df6af89be4fcfcd6d6d36cae0a0362868949
https://github.com/llvm/llvm-project/commit/8a67df6af89be4fcfcd6d6d36cae0a0362868949
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
Log Message:
-----------
[Target] Remove declarations without definitions (NFC) (#225615)
initializeAArch64CFIFixupPass: Added on April 11, 2022 in commit
b4ad28da196d3c2b1bc064b4dc46c3e00e93438f without a definition.
AArch64InstructionSelector::selectReduction: The definition was removed
on November 13, 2023 in commit a604c4b562e99470e397f050f1e8707f923ebed7.
AArch64TargetELFStreamer::insertAttributeInPlace: Added on January 23,
2025 in commit ee99c4d4845db66c4daa2373352133f4b237c942 without a
definition.
ARMInstPrinter::printAM2PostIndexOp: The definition was removed on
September 22, 2012 in commit 2fdbdc58701ef41ab6b52c064723926e6ec4b44f.
ARMMCCodeEmitter::getMachineSoImmOpValue: The definition was removed on
October 12, 2010 in commit 12e493ace4fc5b499361122bc5f25d2c46bea5e4.
ARMMCCodeEmitter::getThumbSRImmOpValue: The definition was removed on
August 17, 2011 in commit 46dd413991f6fa74a1da3f139b386e364dfc9f78.
createAVRBranchSelectionPass: The definition was removed on July 5, 2017
in commit a24aa1990084c15f0ad27dbcff7ab1c96369f0f9.
dxil::DXILOpBuilder::getOpFunctionType: Added on August 2, 2024 in
commit 8cf85653b6f5c90b83f8a5741baad5725d6c6932 without a definition.
dxil::DXILBitcodeWriter::VSTOffsetPlaceholder,
dxil::DXILBitcodeWriter::writeIdentificationBlock,
dxil::DXILBitcodeWriter::writePerModuleFunctionSummaryRecord,
dxil::DXILBitcodeWriter::writeModuleLevelReferences,
dxil::DXILBitcodeWriter::addToStrtab,
dxil::DXILBitcodeWriter::createNamedMetadataAbbrev,
dxil::DXILBitcodeWriter::writeNamedMetadata,
dxil::DXILBitcodeWriter::pushGlobalMetadataAttachment,
dxil::DXILBitcodeWriter::writeOperandBundleTags,
dxil::DXILBitcodeWriter::writeSyncScopeNames,
dxil::DXILBitcodeWriter::writeOperandBundles,
dxil::DXILBitcodeWriter::writeGlobalValueSymbolTable: Added on
April 14, 2022 in commit f2526c1a5c6fe6d2740b68e2d73b85c958fd2719
without uses or definitions.
initializeHexagonMergeActivateWeightPass,
createHexagonMergeActivateWeight: Added on August 5, 2024 in commit
c04857cb2c9f6f2e8add61192c62e48a83938efd without definitions.
createHexagonTargetTransformInfoPass: Added on June 15, 2015 in commit
56efafc0566def51ec7e632e09574ed553296b48 without a definition.
HexagonGlobalSchedulerImpl::CanPromoteToDotNew: Added on February 20,
2026 in commit 7064ff2226141034fdb264c29b97acbc733f8dae without a
definition.
HexagonTargetLowering::LowerANY_EXTEND,
HexagonTargetLowering::LowerSIGN_EXTEND,
HexagonTargetLowering::LowerZERO_EXTEND: The definitions were removed on
February 6, 2018 in commit 8abaf8954a97f20d0fd036e8e32e4b69d23f342e.
HexagonTargetLowering::LowerEH_LABEL: Added on December 12, 2011 in
commit 1213a7a57fdcb6c875b3f79103fc96d3e9d30b40 without a definition.
HexagonPacketizerList::isCurifiable: Added on December 16, 2015 in
commit 56bbf54b4303cac8772b6d66e3bd0668f8013067 without a definition.
HexagonMCChecker::checkBranches: The definition was removed on
December 11, 2017 in commit a8ab1b75cb0d84ea61642d7b7c0139e6e367c28e.
createHexagonMCRegisterInfo: Added on February 6, 2017 in commit
8cdfe8ecf3dd14d128148c5ff0b01d74b082e3c2 without a definition.
HexagonShuffler::restrictNoSlot1: Added on January 17, 2020 in commit
c1873631d0a8f2acca4ab428a1e9abea844d97ff without a definition.
MipsAsmParser::parseImm: The definition was removed on August 8, 2016 in
commit 3feeb9c851a193f42d890b35f36816fae198860f.
MipsAsmParser::validateMSAIndex: The definition was removed on April 1,
2014 in commit b50ccf8e26653781191491aab90c7379f29bd5e1.
MipsMCCodeEmitter::getMSAMemEncoding: The definition was removed on
March 31, 2016 in commit dc0602a2c20a3f514541165a19cb1534597c5dc6.
Mips16DAGToDAGISel::initMips16SPAliasReg: The definition was removed on
June 16, 2016 in commit de7816b0cd3ffbd9775681c408298febe4c10fe3.
MipsAsmPrinter::EmitInstrWithMacroNoAT: The definition was removed on
June 2, 2012 in commit 23327b30ef9af2323dd20248e311ef454f9e0dfa.
MipsTargetLowering::emitSEL_D: The definition was removed on July 20,
2017 in commit be0bc71e023455a32d074b69054b6ffee6f1160e.
MipsSEDAGToDAGISel::selectMULT: The definition was removed on April 11,
2013 in commit 4f1130eb66ff01128c0061ace377c10b74128a45.
MipsSETargetLowering::lowerINT_TO_FP,
MipsSETargetLowering::lowerFP_TO_INT: The definitions were removed on
June 17, 2026 in commit de84e7ccc602fe2ef8b886a9b095c80d110f61a0.
MipsSubtarget::IsLinux: All uses were removed on December 19, 2014 in
commit 8985ba912f00de68f3fccf8bf440a30bf5bdb89e.
MipsSubtarget::OverrideMode, MipsSubtarget::setHelperClassesMips16,
MipsSubtarget::setHelperClassesMipsSE: All uses of OverrideMode and the
definitions of setHelperClassesMips16 and setHelperClassesMipsSE were
removed on July 18, 2014 in commit
4e7d1e7e7bb36bcd715297b36d688bdc0ed96bdf.
initializeNVVMReflectPass: The definition was removed on April 10, 2025
in commit 701d726ef09ea89909df9bd2fdc63c63758fe8d6.
NVPTXDAGToDAGISel::SelectTexSurfHandle: The definition was removed on
June 25, 2025 in commit 70333de6cfa76d2e0e36720d6065edd501a3ad8a.
NVPTXDAGToDAGISel::tryConstantFP: The definition was removed on
December 19, 2024 in commit 310e79875752886a7713911e2a1ec14bc75bd4b3.
NVPTXDAGToDAGISel::SelectCpAsyncBulkTensorReduceCommon: The definition
was removed on August 6, 2026 in commit
1ac19e41a0674925911e88cc5218dfd95a09a3ac.
createPPCMachObjectWriter: The definition was removed on March 2, 2020
in commit 3e851f4a688c42315355aae743b403dddeba9860.
createPPCExpandISELPass: The definition was removed on August 27, 2024
in commit 8e901c255df45e38cb1d69a576804029e20868bf.
SystemZTargetLowering::convertPrevCompareToBranch: The definition was
removed on July 25, 2013 in commit
c3f85d73ab781601b2aababa8ef6572fa437c4ff.
VEAsmParser::parseCCOpOperand: Added on June 5, 2020 in commit
117c0d7c1c12e5c82e0f5498fec511e8ae08d9ca without a definition.
VEAsmParser::parseRDOpOperand: Added on June 10, 2020 in commit
34fef0c980446c3ea9595328e0e525db222870f0 without a definition.
WebAssemblyOptimizeReturnedLegacy::visitCallBase: The definition was
moved to a helper class on July 15, 2026 in commit
491539a8b801aad5706cc32fc54a319791d57a91.
X86FixupInstTuningLegacy::processInstruction: The definition was moved
to a helper class on January 12, 2026 in commit
f6d0a512972a74ef100723b9526a6a0ddb23f894.
XCoreTargetLowering::getReturnAddressFrameIndex: Added on November 7,
2008 in commit ca08e0645a9629980156208506b6ae463b746e42 without a
definition.
Assisted-by: Antigravity
Commit: 748e21a693d24bdd9168fa718a1a5146d414e8b2
https://github.com/llvm/llvm-project/commit/748e21a693d24bdd9168fa718a1a5146d414e8b2
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCDeclareActionConversion.cpp
M flang/test/Fir/OpenACC/declare-action-conversion.fir
M flang/test/Lower/OpenACC/acc-declare-allocatable-deallocate.f90
M flang/test/Lower/OpenACC/acc-declare-unified.f90
M flang/test/Lower/OpenACC/acc-declare-use-associated-allocatable.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M mlir/include/mlir/Conversion/OpenACCToLLVM/ACCToLLVM.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCRuntimeFunctions.def
M mlir/include/mlir/Dialect/OpenACC/OpenACCRuntimeUtils.h
M mlir/lib/Conversion/OpenACCToLLVM/ACCDataDirectivePatterns.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCRuntimeUtils.cpp
A mlir/test/Conversion/OpenACCToLLVM/declare.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
[mlir][acc] Add acc declare codegen to ACCToLLVM (#225557)
Extends the acc to LLVM conversion with codegen for `acc declare`. A
structured declare uses the same data entry points as `acc.data`. An
unstructured declare registers its objects with `__tgt_acc_declare`. A
declare in a declare-action recipe only allocates or frees the device
mirror of an object the host already manages, through
`__tgt_acc_mirror_alloc` and `__tgt_acc_mirror_dealloc`. As with the
other directives, these runtime APIs are not yet finalized; the draft
proposal can be found at
https://github.com/llvm/llvm-project/pull/197894.
Placing the globals that a declare directive names into the device image
is not part of this change.
Co-authored-by: Matsu <kmatsumura at nvidia.com>
Commit: 41ab14be8d53df1df1e46d2a80c37463aeb02a31
https://github.com/llvm/llvm-project/commit/41ab14be8d53df1df1e46d2a80c37463aeb02a31
Author: Konstantinos Parasyris <koparasy at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
A clang/test/CIR/CodeGen/cxx20-module-initializer-ms-abi.cppm
Log Message:
-----------
[CIR] Fix assertion on Microsoft-ABI C++20 named module initializer (#225565)
Compiling a C++20 named module interface unit for the Microsoft C++ ABI
asserts in `LoweringPrepare`, because the AST fallback for the
initializer name does an unguarded `cast<ItaniumMangleContext>`
([LoweringPrepare.cpp#L2006-L2013](https://github.com/llvm/llvm-project/blob/97458f644132d62bb938823394b716b684956f49/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp#L2006-L2013)).
That fallback is reachable because CIRGen only emits
`cir.cxx_module_init_fn_name` for the Itanium mangler
([CIRGenModule.cpp#L3985-L3996](https://github.com/llvm/llvm-project/blob/97458f644132d62bb938823394b716b684956f49/clang/lib/CIR/CodeGen/CIRGenModule.cpp#L3985-L3996)),
mirroring classic codegen's `CXX20ModuleInits`
([CodeGenModule.cpp#L596-L601](https://github.com/llvm/llvm-project/blob/97458f644132d62bb938823394b716b684956f49/clang/lib/CodeGen/CodeGenModule.cpp#L596-L601)).
This deletes the fallback so the attribute is the only channel: absent
means `_GLOBAL__sub_I_` with internal linkage, which is exactly what
classic codegen does for this ABI
([CodeGenModule.cpp#L1205-L1208](https://github.com/llvm/llvm-project/blob/97458f644132d62bb938823394b716b684956f49/clang/lib/CodeGen/CodeGenModule.cpp#L1205-L1208)).
The new test pins that lowering and fails with the same assertion
without the fix. It checks CIR rather than LLVM IR because Microsoft-ABI
CIR cannot reach LLVM IR yet (`EH ABI lowering is not yet implemented
for the Microsoft ABI`). This also drops the last `ASTContext` use in
`buildCXXGlobalInitFunc`.
Commit: 37d97297fd3f1fd8c0c5ba79fc81eddd5553cbbb
https://github.com/llvm/llvm-project/commit/37d97297fd3f1fd8c0c5ba79fc81eddd5553cbbb
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M flang-rt/lib/runtime/derived.cpp
A flang-rt/test/Driver/derived-array-destruction.f90
Log Message:
-----------
[Flang] Restrict the scalar destruction fast path to rank-zero components (#224345)
Restrict the scalar destruction fast path to rank-zero components,
preventing invalid frees for zero-sized derived-type components. Add
regression coverage for scalar and array containers.
Commit: ddf72a3aa679bc2b8b93744443a00d8a6a5dfe50
https://github.com/llvm/llvm-project/commit/ddf72a3aa679bc2b8b93744443a00d8a6a5dfe50
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
Log Message:
-----------
[SLP][NFC]Add a test with the missed vectorization after splats, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225835
Commit: e28d3f11a8ada5012cf28d4a34f9e70c80d6f34e
https://github.com/llvm/llvm-project/commit/e28d3f11a8ada5012cf28d4a34f9e70c80d6f34e
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
Log Message:
-----------
[AMDGPU] Fall back for FP8-to-half conversions without native support (#225528)
The custom `v2i8` source action also handles half results on gfx950,
which has native OCP FP8-to-f32 conversions but lacks FP8-to-f16
instructions. Converting FP8 vectors to half therefore reached
`lowerFromFP8` and asserted that `FP8F16ConversionInsts` was available.
Use generic legalization for half results when the subtarget lacks the
required instructions. Preserve native f32 conversions and native f16
conversions on targets that support them.
Assisted by: Codex (Astra)
Commit: 6b5630dc25728baad8a4daf8697db2da15e7ed58
https://github.com/llvm/llvm-project/commit/6b5630dc25728baad8a4daf8697db2da15e7ed58
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
Log Message:
-----------
[SLP]Do not reorder the tree to match internal gathers of splat subtrees
The internal gathers of the splat gather subtrees are not used as
shuffle sources, but still defined the order of the main tree gathers.
The reorder shuffle stayed after the subtree was dropped as
unprofitable and rejected the profitable tree.
Fixes the perf regression from #220250, reported in #221717.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225839
Commit: f55e761c7fb78381074b07fe7001166c9a1c6019
https://github.com/llvm/llvm-project/commit/f55e761c7fb78381074b07fe7001166c9a1c6019
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
A clang/test/CIR/CodeGen/matrix.cpp
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
A clang/test/CIR/IR/invalid-matrix.cir
A clang/test/CIR/IR/matrix.cir
Log Message:
-----------
[CIR] Support builtin matrix type (#221773)
Implement the basic support for the built-in matrix type
Issue #221772
Commit: dcd8f3442430915048c57164c193513d257e8ace
https://github.com/llvm/llvm-project/commit/dcd8f3442430915048c57164c193513d257e8ace
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/test/CodeGen/Sparc/sparcv8-abi.c
Log Message:
-----------
[Sparc][clang] Match GCC's SPARC V8 vector return convention (#222264)
Match GCC's SPARC V8 calling convention for vector return values. Return
floating-point vectors and vectors larger than 64 bits indirectly.
Return smaller integer vectors in floating-point registers.
Assisted-by: Codex
Commit: 4f5ae89a4a8c49549cd3884c1f42f3fbba8d8ff3
https://github.com/llvm/llvm-project/commit/4f5ae89a4a8c49549cd3884c1f42f3fbba8d8ff3
Author: Harald van Dijk <hdijk at accesssoftek.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M lldb/test/Shell/Settings/Inputs/EchoCommandsAll.out
M lldb/test/Shell/Settings/Inputs/EchoCommandsNoComments.out
M lldb/test/Shell/Settings/Inputs/EchoCommandsNone.out
M llvm/lib/Support/Regex.cpp
M llvm/lib/Support/regcomp.c
A llvm/test/FileCheck/escape.txt
M llvm/unittests/Support/RegexTest.cpp
Log Message:
-----------
[Support] Allow \n, \t, \x in regexes (#223024)
\n and \t were already permitted in Regex::sub, but not in the regex
pattern itself. This commit allows them there too.
\x was not supported at all. This commit allows it both in regex
patterns and in Regex::sub.
The goal is to allow \x to be used in FileCheck patterns and to that
end, a test is also included that this works in FileCheck as expected.
Commit: 4b150e53377a931ab02a2c6b225ccdd75e0d8284
https://github.com/llvm/llvm-project/commit/4b150e53377a931ab02a2c6b225ccdd75e0d8284
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/test/Transforms/GlobalOpt/storepointer.ll
Log Message:
-----------
[GlobalOpt] Use getGetElementPtr() overload accepting a DataLayout (#225789)
To produce the GEP in canonical ptradd form. Unlike other uses,
this one has to take potential failure to create the constant
expression into account.
It also seems like the GEP path was entirely untested, so I added
some basic test coverage for it.
Commit: 7799236d0b84d6fc49a336393aecaba83c061ddf
https://github.com/llvm/llvm-project/commit/7799236d0b84d6fc49a336393aecaba83c061ddf
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[MLIR][XeGPU] Improve multi-reduction layout inference (#224618)
Commit: a9828443a2a90a672551f1f59098393601959ed4
https://github.com/llvm/llvm-project/commit/a9828443a2a90a672551f1f59098393601959ed4
Author: Andrew Haberlandt <ahaberlandt at apple.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M compiler-rt/test/fuzzer/minimize_crash.test
Log Message:
-----------
minimize_crash.test sometimes one-shots the minimization (fix flaky test) (#225544)
After #223470 it is now possible for `minimize_crash.test` to one-shot
the minimization by applying the EraseBytes mutation 3 times (to go from
size 8=>4=>2=>1).
```
| 35: SUMMARY: libFuzzer: deadly signal
| 36: MS: 3 EraseBytes-EraseBytes-EraseBytes-; base unit: 0000000000000000000000000000000000000000
| 37: 0x2a,
| 38: *
```
This causes the test to fail because it only prints the `Test unit
written to` line once. This sets `-mutate_depth` to 2 to guarantee that
it won't be one-shot and thus the line will print more than once.
rdar://188078094
Commit: 7311a69f6caa2a6b50cfb899d4b8a1f9f9eeb210
https://github.com/llvm/llvm-project/commit/7311a69f6caa2a6b50cfb899d4b8a1f9f9eeb210
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/include/llvm/ADT/DepthFirstIterator.h
Log Message:
-----------
[ADT] Use SmallVector in df_iterator. NFC (#225787)
Helps with compile time. The small size of 8 was chosen to match
ReversePostOrderTraversal.
https://llvm-compile-time-tracker.com/compare.php?from=5bb2e21c30de31871dd01279c13abcfa2c06e75f&to=3f3c5680cae30aa33f6988ee8b326b71f5195577&stat=instructions:u
Commit: 4d2fb60d36492c4dfba957d2b726abf9dd30b8fc
https://github.com/llvm/llvm-project/commit/4d2fb60d36492c4dfba957d2b726abf9dd30b8fc
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/include/clang/AST/TypeBase.h
M clang/test/SemaCXX/make_integer_seq.cpp
Log Message:
-----------
[clang] Widen SubstTemplateTypeParmType::PackIndex to 16 bits (#225584)
#132748 narrowed PackIndex to 15 bits when adding Final, leaving a bit
unused, so a type pack with 32768 or more elements stores a wrapped pack
index. The node then keys differently from its lookup, failing the
UniquingSet insert assertion. Restore the 16-bit width, matching
SubstPackType's 16-bit NumArgs.
Fix assertion failure https://godbolt.org/z/9r1jEqqob
Aided by Opus 5.5
Commit: 04fe618233c11703862c114caf33b8c29ef27e13
https://github.com/llvm/llvm-project/commit/04fe618233c11703862c114caf33b8c29ef27e13
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M lldb/source/Plugins/Platform/MacOSX/CMakeLists.txt
M lldb/unittests/Callback/CMakeLists.txt
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Interpreter/CMakeLists.txt
M lldb/unittests/Platform/CMakeLists.txt
M lldb/unittests/Process/CMakeLists.txt
M lldb/unittests/Process/gdb-remote/CMakeLists.txt
M lldb/unittests/Protocol/CMakeLists.txt
M lldb/unittests/Target/CMakeLists.txt
Log Message:
-----------
[lldb] Add Options to LINK_COMPONENTS (#225684)
This fixes shared library build of lldb:
```
/usr/bin/ld: lib/liblldbPluginPlatformMacOSX.a(PlatformDarwin.cpp.o): undefined reference to symbol '_ZNK4llvm3opt8OptTable9getOptionENS0_12OptSpecifierE'
/usr/bin/ld: /work/kparzysz/git/llvm.org/b/x86/lib/libLLVMOption.so.24.0git: error adding symbols: DSO missing from command line
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
```
And several other cases in unittests.
Commit: b33ddc8a951321ee4cc6beda31e1cd0880e8d242
https://github.com/llvm/llvm-project/commit/b33ddc8a951321ee4cc6beda31e1cd0880e8d242
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/fsub-chain-reduction-unpaired-signs.ll
Log Message:
-----------
[SLP][NFC]Add a test with the regressed vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225846
Commit: fc7aa5f819993f102ca2964cb70a28dd021d94af
https://github.com/llvm/llvm-project/commit/fc7aa5f819993f102ca2964cb70a28dd021d94af
Author: Vasileios Porpodas <vasileios.porpodas at amd.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
A llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/ptr_diff.ll
Log Message:
-----------
[SandboxVec][NFC] Precommit test (#225221)
This is a test for a follow-up patch that improves pointer the diff
calculation.
Commit: aced9473c0493aceeab07c97db10dfbd04a667b3
https://github.com/llvm/llvm-project/commit/aced9473c0493aceeab07c97db10dfbd04a667b3
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVLegalizeResourceBinding.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-cvb-srv-uav.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-texture-sampler.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-uav-counter.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizeRegisterBinding-Heap.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizeRegisterBinding-Heap2.ll
Log Message:
-----------
[SPIRV] Add support for dynamic/heap resources (#224488)
Extends the `SPIRVLegalizeImplicitBinding` pass to support heap
resources and renames it to `SPIRVLegalizeImplicitAndHeapBinding`.
The pass scans the module for calls to
`llvm.spv.resource.handlefromheap` and groups them into CBV/SRV/UAV
resources and samplers. Calls to
`llvm.spv.resource.counterhandlefromheap` form a third group.
The SPIR-V backend represents descriptor heaps as unbounded resource
arrays. After resolving implicit bindings, the pass assigns the first
available binding to each heap group in the following order: CBV/SRV/UAV
resources, samplers, and counters.
For each group, the pass will replace the heap intrinsic calls with the
explicit `llvm.spv.resource.handlefrombinding` equivalents using the
assigned binding. The pass does not actually need to create the
unbounded resource-array globals itself. It only needs to assign a
unique array name shared by all resources belonging to the same array.
The existing `SPIRVInstructionSelector` will create the globals.
Because the CBV/SRV/UAV group can contain resources with different
types, the backend represents each unique resource type with a separate
array. These arrays share the same descriptor set and binding, so their
bindings intentionally overlap.
Fixes #208054
Assisted by GPT-5.6 Sol
Commit: e1125b3b32e3404e6d1d2ef4d2a6809f84127727
https://github.com/llvm/llvm-project/commit/e1125b3b32e3404e6d1d2ef4d2a6809f84127727
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Run cannotHoistOrSinkRecipe after cheap checks. NFC (#225797)
cannotHoistOrSinkRecipe traverses blocks in the aliasing checks so can
be expensive. We can save some compile time by deferring it after we do
the cheaper checks.
https://llvm-compile-time-tracker.com/compare.php?from=5bb2e21c30de31871dd01279c13abcfa2c06e75f&to=caeacf1cabb08be3608bd02a9b0e683111ab2c6a&stat=instructions:u
Commit: 50b8b5a101f2b6a4f99dd6cd77396ff0cce990e1
https://github.com/llvm/llvm-project/commit/50b8b5a101f2b6a4f99dd6cd77396ff0cce990e1
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
M clang/tools/offload-arch/OffloadArch.cpp
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.cpp
M llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
M llvm/tools/llvm-offload-wrapper/llvm-offload-wrapper.cpp
M llvm/tools/llvm-reduce/llvm-reduce.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M mlir/lib/Tools/mlir-query/MlirQueryMain.cpp
M mlir/lib/Tools/mlir-reduce/MlirReduceMain.cpp
Log Message:
-----------
[Support] Remove cl::DefaultOption (#225609)
https://reviews.llvm.org/D59746 added cl::DefaultOption so that the
built-in -h could be overridden by llvm-objdump and llvm-readobj, which
have since moved to OptTable. The remaining overrides just call
PrintHelpMessage, so remove them along with the flag. -h and --help
keep working in every tool.
LLM-aided
Commit: 59e62a974c22185003286ee03f35a1ea00678d28
https://github.com/llvm/llvm-project/commit/59e62a974c22185003286ee03f35a1ea00678d28
Author: Karim Alweheshy <karim.alweheshy at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/test/tools/llvm-profdata/Inputs/CSIR_profile.proftext
M llvm/test/tools/llvm-profdata/Inputs/IR_profile.proftext
M llvm/test/tools/llvm-profdata/Inputs/cs.proftext
M llvm/test/tools/llvm-profdata/Inputs/instr-remap.expected
M llvm/test/tools/llvm-profdata/merge-filter.test
A llvm/test/tools/llvm-profdata/text-zero-bitmap.test
Log Message:
-----------
[InstrProf] Disambiguate zero bitmaps in text profiles (#213906)
Commit: 680fb32b0ebcf38431579b813613a2949e4d5d6b
https://github.com/llvm/llvm-project/commit/680fb32b0ebcf38431579b813613a2949e4d5d6b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/load-combine.ll
Log Message:
-----------
[X86] load-combine.ll - cleanup check prefixes and don't scrub stack math (#225762)
Ensure all stack addresses are visible
Commit: 6f8bca0ce541374893a7e0b2b64d383f515ca632
https://github.com/llvm/llvm-project/commit/6f8bca0ce541374893a7e0b2b64d383f515ca632
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-srv-load.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll
Log Message:
-----------
[DirectX] Set TypedUAVLoadAdditionalFormats on UAV texture loads (#225484)
Fixes https://github.com/llvm/llvm-project/issues/225147
This PR makes the `TypedUAVLoadAdditionalFormats` shader flag get set on
UAV texture loads.
Assisted by: GPT 5.6 Sol
Commit: 9c3693b6b1ceeeb4c00e9b03bcb1c646b8c9dd6a
https://github.com/llvm/llvm-project/commit/9c3693b6b1ceeeb4c00e9b03bcb1c646b8c9dd6a
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-23 (Wed, 23 Sep 2026)
Changed paths:
M .github/workflows/libcxx-benchmark-commit.yml
M .github/workflows/libcxx-pr-benchmark.yml
M .github/workflows/libcxx-pr-test-tools.yml
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/lib/AST/ByteCode/ByteCodeEmitter.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpHelpers.h
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/LoweringHelpers.cpp
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/CIR/CodeGen/base-init-eh.cpp
M clang/test/CIR/CodeGen/ctor-null-init.cpp
A clang/test/CIR/CodeGen/cxx20-module-initializer-ms-abi.cppm
M clang/test/CIR/CodeGen/delegating-ctor.cpp
M clang/test/CIR/CodeGen/destructor-vtable-reinit.cpp
M clang/test/CIR/CodeGen/global-ptr-init.cpp
M clang/test/CIR/CodeGen/inherited-ctors.cpp
A clang/test/CIR/CodeGen/matrix.cpp
M clang/test/CIR/CodeGen/multi-vtable.cpp
M clang/test/CIR/CodeGen/rtti-member-pointer.cpp
M clang/test/CIR/CodeGen/rtti-qualfn.cpp
M clang/test/CIR/CodeGen/side-effect.cpp
M clang/test/CIR/CodeGen/vbase.cpp
M clang/test/CIR/CodeGen/virtual-function-calls.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/CodeGenCXX/base-layout.cpp
M clang/test/CIR/CodeGenCXX/vtable-pure-deleted-funcs.cpp
M clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl
A clang/test/CIR/IR/invalid-matrix.cir
A clang/test/CIR/IR/matrix.cir
A clang/test/CIR/Transforms/abi-lowering/memory-effects-argmem-indirect.cir
A clang/test/CIR/Transforms/abi-lowering/memory-effects-argmem.cir
M clang/test/CodeGen/Sparc/sparcv8-abi.c
M clang/test/OffloadTools/clang-linker-wrapper/linker-wrapper-image.c
M clang/test/SemaCXX/make_integer_seq.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
M clang/tools/offload-arch/OffloadArch.cpp
M compiler-rt/test/fuzzer/minimize_crash.test
M flang-rt/lib/runtime/derived.cpp
A flang-rt/test/Driver/derived-array-destruction.f90
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCDeclareActionConversion.cpp
M flang/test/Fir/OpenACC/declare-action-conversion.fir
M flang/test/Lower/OpenACC/acc-declare-allocatable-deallocate.f90
M flang/test/Lower/OpenACC/acc-declare-unified.f90
M flang/test/Lower/OpenACC/acc-declare-use-associated-allocatable.f90
M flang/test/Lower/OpenACC/acc-declare.f90
A flang/test/Lower/io-implied-do-collapse.f90
M libcxx/utils/ci/lnt/README.md
M libcxx/utils/ci/lnt/machines.json
M libcxx/utils/ci/lnt/run-benchmarks
M libcxx/utils/ci/run-buildbot
M lldb/source/Plugins/Platform/MacOSX/CMakeLists.txt
M lldb/test/Shell/Settings/Inputs/EchoCommandsAll.out
M lldb/test/Shell/Settings/Inputs/EchoCommandsNoComments.out
M lldb/test/Shell/Settings/Inputs/EchoCommandsNone.out
M lldb/unittests/Callback/CMakeLists.txt
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Interpreter/CMakeLists.txt
M lldb/unittests/Platform/CMakeLists.txt
M lldb/unittests/Process/CMakeLists.txt
M lldb/unittests/Process/gdb-remote/CMakeLists.txt
M lldb/unittests/Protocol/CMakeLists.txt
M lldb/unittests/Target/CMakeLists.txt
M llvm/docs/CommandLine.md
M llvm/include/llvm/ADT/DepthFirstIterator.h
M llvm/include/llvm/ExecutionEngine/JITLink/ELF_aarch64.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch64.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch64.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/Regex.cpp
M llvm/lib/Support/regcomp.c
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h
M llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
M llvm/lib/Target/AVR/AVR.h
M llvm/lib/Target/DirectX/DXILOpBuilder.h
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
M llvm/lib/Target/Hexagon/Hexagon.h
M llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
M llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/lib/Target/Mips/MipsSubtarget.h
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/SPIRV/SPIRVLegalizeResourceBinding.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.cpp
M llvm/lib/Target/SPIRV/SPIRVNonSemanticDebugHandler.h
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.h
M llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyOptimizeReturned.cpp
M llvm/lib/Target/X86/X86FixupInstTuning.cpp
M llvm/lib/Target/XCore/XCoreISelLowering.h
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
M llvm/test/Analysis/ScalarEvolution/ptrtoaddr-i32-index-width.ll
M llvm/test/CodeGen/AMDGPU/arbitrary-fp-from-float-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir
A llvm/test/CodeGen/AMDGPU/coexec-sched-barrier-latency.mir
A llvm/test/CodeGen/AMDGPU/finalize-isel-vadd-co-u32-dead-carry.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
M llvm/test/CodeGen/AMDGPU/ldsdmacnt_sched.mir
A llvm/test/CodeGen/AMDGPU/move-scalar-carry-to-valu-dead-vcc.mir
M llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
M llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-srv-load.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt
M llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
A llvm/test/CodeGen/Mips/fpu-delay-in-delay-slot.ll
M llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll
M llvm/test/CodeGen/Mips/llvm-ir/load.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
M llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
A llvm/test/CodeGen/Mips/mips1-fpu-load-delay.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-declare-dbg-value-variadic.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-declare.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-inlined-at.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-line-selection-merge.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-local-variable-dbg-value.ll
M llvm/test/CodeGen/SPIRV/debug-info/debug-type-pointer.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant-existing-type.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-constant.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-cross-block.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-merge-region.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-module-scope.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-postlegalizer-order.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-typedef-cycle.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value-unsupported.ll
A llvm/test/CodeGen/SPIRV/debug-info/debug-value.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-cvb-srv-uav.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-texture-sampler.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/HeapBinding-uav-counter.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizeRegisterBinding-Heap.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVLegalizeRegisterBinding-Heap2.ll
M llvm/test/CodeGen/X86/load-combine.ll
A llvm/test/ExecutionEngine/JITLink/AArch64/ELF_ehframe_be.s
A llvm/test/ExecutionEngine/JITLink/AArch64/ELF_relocations_be.s
A llvm/test/FileCheck/escape.txt
M llvm/test/Transforms/GlobalOpt/storepointer.ll
M llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.dot.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.sudot.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/extract-fmul-cost.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/fsub-chain-reduction-unpaired-signs.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-reuse.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/store-chain-leading-slice-wider-vf.ll
A llvm/test/Transforms/SandboxVectorizer/Passes/LoadStoreVec/ptr_diff.ll
M llvm/test/tools/llvm-offload-wrapper/coff-opt-ref.ll
M llvm/test/tools/llvm-profdata/Inputs/CSIR_profile.proftext
M llvm/test/tools/llvm-profdata/Inputs/IR_profile.proftext
M llvm/test/tools/llvm-profdata/Inputs/cs.proftext
M llvm/test/tools/llvm-profdata/Inputs/instr-remap.expected
M llvm/test/tools/llvm-profdata/merge-filter.test
A llvm/test/tools/llvm-profdata/text-zero-bitmap.test
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.cpp
M llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
M llvm/tools/llvm-offload-wrapper/llvm-offload-wrapper.cpp
M llvm/tools/llvm-reduce/llvm-reduce.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Support/RegexTest.cpp
M mlir/include/mlir/Conversion/OpenACCToLLVM/ACCToLLVM.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCRuntimeFunctions.def
M mlir/include/mlir/Dialect/OpenACC/OpenACCRuntimeUtils.h
M mlir/lib/Conversion/OpenACCToLLVM/ACCDataDirectivePatterns.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCRuntimeUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp
M mlir/lib/Tools/mlir-query/MlirQueryMain.cpp
M mlir/lib/Tools/mlir-reduce/MlirReduceMain.cpp
A mlir/test/Conversion/OpenACCToLLVM/declare.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCOpsInterfacesTest.cpp
Log Message:
-----------
Merge branch 'main' into users/adams381/cir-callconv-nonbyval-param-noload
Compare: https://github.com/llvm/llvm-project/compare/1ff67116663d...9c3693b6b1ce
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