[all-commits] [llvm/llvm-project] 95f6c4: [AMDGPU] Add MemoryPipeline scheduling to Coexec s...

[Austin Kerbow via All-commits]

  Branch: refs/heads/users/jebyrnes/FenceWaitRebase2
  Home:   https://github.com/llvm/llvm-project
  Commit: 95f6c4aecb9e4d824a58f333f17664ba76037b68
      https://github.com/llvm/llvm-project/commit/95f6c4aecb9e4d824a58f333f17664ba76037b68
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  [AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5


  Commit: 90d1e968f764a9ff58b67bb0faeb063a4c499029
      https://github.com/llvm/llvm-project/commit/90d1e968f764a9ff58b67bb0faeb063a4c499029
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484


  Commit: c63251b91d8690b5afefafb9debb210f9b63a284
      https://github.com/llvm/llvm-project/commit/c63251b91d8690b5afefafb9debb210f9b63a284
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b


  Commit: 14fe2c9cb50c1f04f81732efab7e8978586f0d59
      https://github.com/llvm/llvm-project/commit/14fe2c9cb50c1f04f81732efab7e8978586f0d59
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f


  Commit: fc2afb141f07bebde5d2af9600e89da97cf5d145
      https://github.com/llvm/llvm-project/commit/fc2afb141f07bebde5d2af9600e89da97cf5d145
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133


  Commit: 8392901a73d8fc613d08d79e18d1752114a45e96
      https://github.com/llvm/llvm-project/commit/8392901a73d8fc613d08d79e18d1752114a45e96
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044


  Commit: 8104bc67cbf6e2f9816697b1ee1c73398dbdb3f8
      https://github.com/llvm/llvm-project/commit/8104bc67cbf6e2f9816697b1ee1c73398dbdb3f8
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e


  Commit: 2921200e6681433e4263ada21c4a1927574fe627
      https://github.com/llvm/llvm-project/commit/2921200e6681433e4263ada21c4a1927574fe627
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Address comments.

Avoid prioritizing DMA and fence candidates while they still have an effective stall.

Make the top-down requirement explicit and remove unreachable bottom-up handling.


Compare: https://github.com/llvm/llvm-project/compare/81c7e6e44c42...2921200e6681

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