[all-commits] [llvm/llvm-project] 02f675: [AMDGPU] Fix overlapping insert crash during rewri...

Fri Sep 11 11:35:59 PDT 2026

  Branch: refs/heads/users/dhruvachak/issue-204224
  Home:   https://github.com/llvm/llvm-project
  Commit: 02f6756911fcebc1d380ff731e0d40832e370b4a
      https://github.com/llvm/llvm-project/commit/02f6756911fcebc1d380ff731e0d40832e370b4a
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
    A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir

  Log Message:
  -----------
  [AMDGPU] Fix overlapping insert crash during rewrite-agpr-copy-mfma

Fixes https://github.com/llvm/llvm-project/issues/204224

Guard against a possibly wrong interference result for a discontiguous
stack slot interval by using the entire range.

A spilled stack slot can have a discontiguous live interval, e.g. a single
value live across several disjoint segments:

  [a, b)  [c, d)  ........gap........  [e, f)

with gaps where the slot is dead. The interference check previously only
considered the covered segments, so it could pick a PhysReg that is free
within them but busy inside a gap. Unspilling replaces the slot with a vreg
whose recomputed interval is continuous over [a, f) (it fills the gaps),
so assigning that PhysReg could overlap the value live in the gap and trip
the "Overlapping insert" assertion in LiveRegMatrix::assign. Checking
interference over the whole [a, f) hull avoids this.

Assisted-by: Cursor/Claude Opus

  Commit: 29a16555daa0ad3a7fca798c4c9e264f857f3208
      https://github.com/llvm/llvm-project/commit/29a16555daa0ad3a7fca798c4c9e264f857f3208
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

  Log Message:
  -----------
  Use checkInterference directly on begin and end slot-index.

  Commit: e59947f2a24253648d5cc7ca366908e8c32c9d11
      https://github.com/llvm/llvm-project/commit/e59947f2a24253648d5cc7ca366908e8c32c9d11
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir

  Log Message:
  -----------
  Use new triple format, remove unnecessary attribute.

  Commit: 66e8146f88f5436755a8ca3cf3f0834ef8a252cc
      https://github.com/llvm/llvm-project/commit/66e8146f88f5436755a8ca3cf3f0834ef8a252cc
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

  Log Message:
  -----------
  Fixed lit test failure
inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir.

  Commit: be682f8a9f0f87cd8f140bb077f8ef0045d49fd8
      https://github.com/llvm/llvm-project/commit/be682f8a9f0f87cd8f140bb077f8ef0045d49fd8
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

  Log Message:
  -----------
  Revert "Fixed lit test failure"

This reverts commit 63dea4d3ed2de9f21093bbe13600e992be513ed6.

  Commit: f94d461ec5202c47b702d2ec73d96a898ad935b5
      https://github.com/llvm/llvm-project/commit/f94d461ec5202c47b702d2ec73d96a898ad935b5
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-unspill-regunit-interference.mir

  Log Message:
  -----------
  Added test for regunit case for checkInterference.

  Commit: 1e5b84f8a5ed1a5ce41ddef314a5fc8634061b16
      https://github.com/llvm/llvm-project/commit/1e5b84f8a5ed1a5ce41ddef314a5fc8634061b16
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-unspill-regmask-interference.mir

  Log Message:
  -----------
  test for regmask.

  Commit: bc3422439b02a077ed7b5901c74b31a3cb174776
      https://github.com/llvm/llvm-project/commit/bc3422439b02a077ed7b5901c74b31a3cb174776
  Author: Dhruva Chakrabarti <Dhruva.Chakrabarti at amd.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveRegMatrix.h
    M llvm/lib/CodeGen/LiveRegMatrix.cpp

  Log Message:
  -----------
  Fix bugs in slot-index-based checkInterference and use for unspill.

Rather than constructing a temporary "hull" LiveInterval and calling the
LiveInterval-based checkInterference overload -- which risks a query-cache
identity hazard when that temporary interval is stack-allocated and reused
across the AllocOrder loop (see the FIXME comment in
LiveRegMatrix::checkInterference(SlotIndex, SlotIndex, MCRegister)) -- this
patch switches the unspilling code to call the slot-index-based
checkInterference(SlotIndex, SlotIndex, MCRegister) overload directly with
the hull's [beginIndex, endIndex).

Doing so exposed a real bug in that overload: LiveRegMatrix.h documents
that returning false means "PhysReg is free at [Start, End)", but the
implementation only checked the matrix of already-assigned virtual
registers. It never checked fixed register-unit interference (e.g. PhysReg
is defined directly by some instruction in [Start, End)) or regmask
interference (e.g. PhysReg is clobbered by a call in [Start, End)) -- both
of which the LiveInterval-based overload does check. This patch adds both
checks to the slot-index-based overload, in the same priority order
(regmask -> regunit -> matrix) as the LiveInterval-based one, bringing the
two implementations in line.

(Note: checkInterferenceLanes(SlotIndex, SlotIndex, MCRegister) has the
same matrix-only shape, but is out of scope for this patch -- it has a
single caller with different semantics.)

Prior to this patch, the only callers of the slot-index-based
checkInterference were two call sites in InlineSpiller
(hoistSpillInsideBB, hasPhysRegAvailable). Both check narrow windows by
construction (a block's PHI/label/debug prologue, or a single instruction
boundary), which is likely why missing regunit/regmask coverage there
hasn't caused any existing LIT test to regress.

Three new tests:
- rewrite-vgpr-mfma-to-agpr-spill-discontiguous-interval.mir: adapted
  from https://github.com/llvm/llvm-project/issues/204224. Verifies we no
  longer crash when there is interference
  inside the gap between a discontiguous stack slot's live segments.
- rewrite-vgpr-mfma-to-agpr-unspill-regunit-interference.mir: a stack
  slot value is live across a block of instructions that directly define
  every VGPR. Without the new regunit check, the slot is wrongly unspilled
  into a clobbered register, and the CHECK lines fail.
- rewrite-vgpr-mfma-to-agpr-unspill-regmask-interference.mir: same
  scenario, but the value is live across a call whose regmask
  (amdgpu_allagprs, a synthetic mask that preserves only AGPRs, used here
  to reliably clobber every VGPR) clobbers the register. Without the new
  regmask check, the unspill proceeds, and either the CHECK lines fail or
  the machine verifier reports a use of an undefined physical register.

Compare: https://github.com/llvm/llvm-project/compare/7ebc816a7aa6...bc3422439b02

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