[all-commits] [llvm/llvm-project] 173a02: [MLIR][LLVM] Enable strict property assembly forma...
Chinmay Deshpande via All-commits
all-commits at lists.llvm.org
Wed Sep 9 15:36:57 PDT 2026
Branch: refs/heads/users/chinmaydd/lds-bank-split
Home: https://github.com/llvm/llvm-project
Commit: 173a02c755bf91fecf90ac4df972128baea91da8
https://github.com/llvm/llvm-project/commit/173a02c755bf91fecf90ac4df972128baea91da8
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M flang/test/Driver/tco-test-gen.fir
M flang/test/Fir/convert-nontemporal-to-llvm.fir
M flang/test/Fir/convert-to-llvm-access-group.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/tbaa.fir
M flang/test/Fir/vector-always-cfg.fir
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMOps.h
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ComplexToLLVM/complex-range-option.mlir
M mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
M mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir
M mlir/test/Conversion/GPUCommon/transfer_write.mlir
M mlir/test/Conversion/MathToLLVM/math-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-load-store-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-xfer-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/bytecode.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/dereferenceable-invalid.mlir
M mlir/test/Dialect/LLVMIR/ifunc.mlir
M mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
M mlir/test/Dialect/LLVMIR/inlining-loop-annotation.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/LLVMIR/opaque-ptr.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/LLVMIR/tbaa-roundtrip.mlir
M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
M mlir/test/Dialect/Vector/vector-transpose-to-matrix-intrinsics-transform.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-row.mlir
M mlir/test/Target/LLVMIR/Import/fastmath.ll
M mlir/test/Target/LLVMIR/Import/ifunc.ll
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/Import/masked-intrinsic-metadata.ll
M mlir/test/Target/LLVMIR/Import/metadata-loop.ll
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/Import/metadata-tbaa.ll
M mlir/test/Target/LLVMIR/Import/target-ext-type.ll
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction_teams.mlir
M mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
M mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
M mlir/test/Target/LLVMIR/attribute-dereferenceable.mlir
M mlir/test/Target/LLVMIR/attribute-tbaa.mlir
M mlir/test/Target/LLVMIR/ifunc.mlir
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/loop-metadata.mlir
M mlir/test/Target/LLVMIR/masked-intrinsic-metadata.mlir
M mlir/test/Target/LLVMIR/omptarget-debug-record-pos.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-nowait.mlir
M mlir/test/Target/LLVMIR/opaque-ptr.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-nontemporal.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
M mlir/test/Target/LLVMIR/openmp-simd-private.mlir
M mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
M mlir/test/Target/LLVMIR/openmp-target-private.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir
M mlir/test/Target/LLVMIR/target-ext-type.mlir
M mlir/test/mlir-tblgen/op-format.td
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
[MLIR][LLVM] Enable strict property assembly format (#217277)
Enable strict property assembly format mode for the LLVM dialect. Bind
LLVM operation properties directly in declarative assembly formats so
strict parsing does not rely on fallback handling.
Update LLVM dialect, target, and conversion tests to use the direct
property spelling.
Assisted-by: Codex
Commit: b1b68627b9da8d4bbdf9a39bb2bde52dd6ce8bf3
https://github.com/llvm/llvm-project/commit/b1b68627b9da8d4bbdf9a39bb2bde52dd6ce8bf3
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/CMakeLists.txt
M llvm/CMakeLists.txt
Log Message:
-----------
[CIR][CMake] Configure MLIR as a dependency-only project (#221739)
Enable MLIR implicitly for ClangIR without attaching its unrelated tools
and test suite to the aggregate build. An explicit MLIR selection
retains its normal behavior. Add MLIR after all Clang consumers enable
Clang, so CIR also works when Clang is enabled for LLDB.
Package the required MLIR libraries through Clang's existing exports and
LLVM's distribution policy. Register dependency library and header
install components and honor toolchain-only installations. When Clang is
itself an implicit Flang dependency, let Flang package the required
targets.
Keep MLIR test support available for CIR and retain the standalone
ClangIR restriction. Leave MLIR disabled when CIR is disabled.
Assisted-by: Codex
Commit: e6114dbeed424ce7c483000e181f97b962a56fe7
https://github.com/llvm/llvm-project/commit/e6114dbeed424ce7c483000e181f97b962a56fe7
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/PipelineDataTransfer.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeVectorStorage.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/SCF/Transforms/ForallToParallel.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDropLeadUnitDim.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/Vector/linearize.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/Transforms/scf-replace-with-new-yields.mlir
M mlir/test/lib/Dialect/SCF/TestLoopUnrolling.cpp
M mlir/test/lib/Dialect/SCF/TestParallelLoopUnrolling.cpp
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
Log Message:
-----------
[mlir][Affine][SCF][Vector] Migrate to split inherent/discardable attribute APIs (#218913)
Migrate the Affine, Arith, Arm vector, SCF, and Vector dialect families
and related conversions to explicit discardable or typed attribute
access.
Assisted-by: Codex
Commit: 97d5de84b6936c6366a0e184211f683b43e73429
https://github.com/llvm/llvm-project/commit/97d5de84b6936c6366a0e184211f683b43e73429
Author: Akash Dutta <137309513+akadutta at users.noreply.github.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU][NFC] Simplify conditional return in SIInstrInfo.cpp (#222426)
Commit: d3db069999553568848400c84cbf815c03f5470f
https://github.com/llvm/llvm-project/commit/d3db069999553568848400c84cbf815c03f5470f
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-strict.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/MC/AMDGPU/gfx1250-strict_err.s
Log Message:
-----------
[AMDGPU] Disable wmma_*_f4 instructions for gfx1250-strict (#222434)
Commit: 8977e12f8eb3e4af3b00efca4a765a434e2ecf27
https://github.com/llvm/llvm-project/commit/8977e12f8eb3e4af3b00efca4a765a434e2ecf27
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-09 (Wed, 09 Sep 2026)
Changed paths:
M clang/CMakeLists.txt
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-strict.cl
M flang/test/Driver/tco-test-gen.fir
M flang/test/Fir/convert-nontemporal-to-llvm.fir
M flang/test/Fir/convert-to-llvm-access-group.fir
M flang/test/Fir/convert-to-llvm.fir
M flang/test/Fir/tbaa.fir
M flang/test/Fir/vector-always-cfg.fir
M llvm/CMakeLists.txt
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/MC/AMDGPU/gfx1250-strict_err.s
M mlir/docs/SPIRVToLLVMDialectConversion.md
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMDialect.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.cpp
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToGPU/SCFToGPU.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Dialect/Affine/Analysis/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/PipelineDataTransfer.cpp
M mlir/lib/Dialect/Affine/Transforms/SimplifyAffineStructures.cpp
M mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Arith/Transforms/EmulateUnsupportedFloats.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Arith/Transforms/UnsignedWhenEquivalent.cpp
M mlir/lib/Dialect/ArmSME/Transforms/EnableArmStreaming.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeVectorStorage.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMOps.h
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/SCF/Transforms/ForallToParallel.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDropLeadUnitDim.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ComplexToLLVM/complex-range-option.mlir
M mlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
M mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir
M mlir/test/Conversion/GPUCommon/transfer_write.mlir
M mlir/test/Conversion/MathToLLVM/math-to-llvm.mlir
M mlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
M mlir/test/Conversion/SPIRVToLLVM/memory-ops-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-load-store-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-reduction-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/vector-xfer-to-llvm.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_1d.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Arith/unsigned-when-equivalent.mlir
M mlir/test/Dialect/LLVMIR/bytecode.mlir
M mlir/test/Dialect/LLVMIR/canonicalize.mlir
M mlir/test/Dialect/LLVMIR/dereferenceable-invalid.mlir
M mlir/test/Dialect/LLVMIR/ifunc.mlir
M mlir/test/Dialect/LLVMIR/inlining-alias-scopes.mlir
M mlir/test/Dialect/LLVMIR/inlining-loop-annotation.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-intrinsics.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/LLVMIR/opaque-ptr.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/LLVMIR/tbaa-roundtrip.mlir
M mlir/test/Dialect/SCF/ops.mlir
M mlir/test/Dialect/Vector/linearize.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Dialect/Vector/vector-contract-to-matrix-intrinsics-transforms.mlir
M mlir/test/Dialect/Vector/vector-dropleadunitdim-transforms.mlir
M mlir/test/Dialect/Vector/vector-transpose-to-matrix-intrinsics-transform.mlir
M mlir/test/Dialect/Vector/vector-unroll-options.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/flat-transpose-row.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-col.mlir
M mlir/test/Integration/Dialect/Vector/CPU/matrix-multiply-row.mlir
M mlir/test/Target/LLVMIR/Import/fastmath.ll
M mlir/test/Target/LLVMIR/Import/ifunc.ll
M mlir/test/Target/LLVMIR/Import/instructions.ll
M mlir/test/Target/LLVMIR/Import/intrinsic.ll
M mlir/test/Target/LLVMIR/Import/masked-intrinsic-metadata.ll
M mlir/test/Target/LLVMIR/Import/metadata-loop.ll
M mlir/test/Target/LLVMIR/Import/metadata-profiling.ll
M mlir/test/Target/LLVMIR/Import/metadata-tbaa.ll
M mlir/test/Target/LLVMIR/Import/target-ext-type.ll
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction.mlir
M mlir/test/Target/LLVMIR/allocatable_gpu_reduction_teams.mlir
M mlir/test/Target/LLVMIR/anonymous-tbaa.mlir
M mlir/test/Target/LLVMIR/attribute-alias-scopes.mlir
M mlir/test/Target/LLVMIR/attribute-dereferenceable.mlir
M mlir/test/Target/LLVMIR/attribute-tbaa.mlir
M mlir/test/Target/LLVMIR/ifunc.mlir
M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/loop-metadata.mlir
M mlir/test/Target/LLVMIR/masked-intrinsic-metadata.mlir
M mlir/test/Target/LLVMIR/omptarget-debug-record-pos.mlir
M mlir/test/Target/LLVMIR/omptarget-multi-reduction.mlir
M mlir/test/Target/LLVMIR/omptarget-nowait.mlir
M mlir/test/Target/LLVMIR/opaque-ptr.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-nontemporal.mlir
M mlir/test/Target/LLVMIR/openmp-reduction-sections.mlir
M mlir/test/Target/LLVMIR/openmp-simd-private.mlir
M mlir/test/Target/LLVMIR/openmp-simd-reduction-simple.mlir
M mlir/test/Target/LLVMIR/openmp-target-private.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-private.mlir
M mlir/test/Target/LLVMIR/target-ext-type.mlir
M mlir/test/Transforms/scf-replace-with-new-yields.mlir
M mlir/test/lib/Dialect/SCF/TestLoopUnrolling.cpp
M mlir/test/lib/Dialect/SCF/TestParallelLoopUnrolling.cpp
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
M mlir/test/mlir-tblgen/op-format.td
M mlir/tools/mlir-tblgen/OpFormatGen.cpp
Log Message:
-----------
Merge branch 'main' into users/chinmaydd/lds-bank-split
Compare: https://github.com/llvm/llvm-project/compare/ef153c816296...8977e12f8eb3
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list