[all-commits] [llvm/llvm-project] 3ae9fa: [AMDGPU] Introduce Offset field in SGPR spill Pseudos

Fri Jul 31 02:32:15 PDT 2026

  Branch: refs/heads/users/cdevadas/putback-ProperlyAlighedRC
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ae9fa55b019438cef9575e252b8a212122316d3
      https://github.com/llvm/llvm-project/commit/3ae9fa55b019438cef9575e252b8a212122316d3
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
    M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
    M llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
    M llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-empty-prolog-block.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/splitkit.mir
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
    M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir

  Log Message:
  -----------
  [AMDGPU] Introduce Offset field in SGPR spill Pseudos

Currently, SGPR spill pseudo-instructions lack
an offset field to represent non-zero stack offsets.
This patch introduces an additional offset field to
SGPR spill pseudo-instructions and updates all
relevant passes that handle spill lowering to support
this new field. This field is essential for a future
patch that implements subreg reload of tuple registers
from their stack location during RA.

  Commit: 1ba3503f8464ac617c840e2b37d41d863a7b36cf
      https://github.com/llvm/llvm-project/commit/1ba3503f8464ac617c840e2b37d41d863a7b36cf
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

  Log Message:
  -----------
  incorporated review comments.

  Commit: 2f15df22b2394cf8a0d09e18238209ce9de4a84d
      https://github.com/llvm/llvm-project/commit/2f15df22b2394cf8a0d09e18238209ce9de4a84d
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h

  Log Message:
  -----------
  [AMDGPU] Make getNumSubRegsForSpillOp externally available (NFC).

  Commit: 7cae9252823a45e86ea23244129d40b2d7ee1da9
      https://github.com/llvm/llvm-project/commit/7cae9252823a45e86ea23244129d40b2d7ee1da9
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h

  Log Message:
  -----------
  moved the implementation to SIInstrInfo.

  Commit: 144d8a2877a431949d350fec6ed24139d2859097
      https://github.com/llvm/llvm-project/commit/144d8a2877a431949d350fec6ed24139d2859097
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h

  Log Message:
  -----------
  fixed a comment.

  Commit: 1687f980476c59a7b381cf262ea77a40fe3266ff
      https://github.com/llvm/llvm-project/commit/1687f980476c59a7b381cf262ea77a40fe3266ff
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

  Log Message:
  -----------
  [AMDGPU] Make AMDGPURewriteAGPRCopyMFMA aware of subreg reload

AMDGPURewriteAGPRCopyMFMA pass is currently not subreg-aware.
In particular, the logic that optimizes spills into COPY
instructions assumes full register reloads. This becomes
problematic when the reload instruction partially restores
a tuple register. This patch introduces the necessary changes
to make this pass subreg-aware, for a future patch that
implements subreg reload during RA.

  Commit: a8e52977d7383770d2864d5afe2769993bdb86b4
      https://github.com/llvm/llvm-project/commit/a8e52977d7383770d2864d5afe2769993bdb86b4
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

  Log Message:
  -----------
  suggestions incorporated.

  Commit: 4343cad32c10a45defe7feba63df493d3e18d13a
      https://github.com/llvm/llvm-project/commit/4343cad32c10a45defe7feba63df493d3e18d13a
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveRangeEdit.h
    M llvm/lib/CodeGen/LiveRangeEdit.cpp

  Log Message:
  -----------
  [CodeGen] Enhance createFrom for sub-reg aware cloning

Instead of just cloning the virtual register, this
function now creates a new virtual register derived
from a subregister class of the original value.

  Commit: c74c50e647a667b34c47e035964c37be2aec5243
      https://github.com/llvm/llvm-project/commit/c74c50e647a667b34c47e035964c37be2aec5243
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2026-01-13 (Tue, 13 Jan 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h

  Log Message:
  -----------
  [AMDGPU] Put back ProperlyAlighedRC helper functions

Putting back the functions that are recently deleted
as they were found unused. They are needed for
implementing subreg reload during RA.

Compare: https://github.com/llvm/llvm-project/compare/3ae9fa55b019%5E...c74c50e647a6

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