[all-commits] [llvm/llvm-project] 81cd5b: [lldb] Convert generic register names in a case in...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 81cd5b6217f12ada97e0f1791ba8545120c13230
      https://github.com/llvm/llvm-project/commit/81cd5b6217f12ada97e0f1791ba8545120c13230
  Author: David Spickett <david.spickett at arm.com>
  Date:   2026-07-31 (Fri, 31 Jul 2026)

  Changed paths:
    M lldb/source/Utility/Args.cpp
    M lldb/test/API/commands/register/register_command/TestRegisters.py

  Log Message:
  -----------
  [lldb] Convert generic register names in a case insensitive way (#213001)

Part of #212778.

There are 3 types of register name:
* The primary name, displayed by default.
* An optional alias, for example AArch64 "lr" is also "x30".
* Generic convenience names like "sp", "ra" and so on.

The first two types are handled case insensitively, but generic names
were not. For example:
(lldb) register read RA
error: Invalid register name 'RA'
(lldb) register read ra
  lr = 0x0000fffff7e27400

In this change I've fixed that.

This does close a workaround for #212778, where you could get to the
actual x86_64 "sp" by using "sP". However, this is only known to work on
Linux, and other architectures are negatively impacted by the bug so I'm
fixing it.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications